博碩士論文 85344009 詳細資訊




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姓名 陳雨蒼(Yue-Tsang Chen)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 混波測試匯流排的量測學
(Metrology for Mixed-Signal Test Bus)
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摘要(中) 為能有效的解決因使用美國電子電機工程學會(IEEE)所制定的1149.4-混波測試匯流排(Mixed-Signal Test Bus)所造成的寄生效應(parasitic effect)與交談失真(crosstalk),因此提出一個能移除這些效應的抽取演算法則,此法則我們稱為本質響應抽取(Intrinsic response extraction)技術。這裡所稱的本質響應是指在沒有寄生效應與交談失真的影響下,由理想輸入信號所獲得的被測電路輸出響應。我們利用deconvolution的技術,可以將理想的輸出響應,由被寄生效應及交談失真所污染的結果中分離出來,由HSPICE模擬程式所獲得的結果可以證明,不論寄生效應、交談失真或輸入信號發生改變,其所獲得的本質響應仍可維持原來的波形。除了模擬驗證外,我們更進一步的利用由1149.4工作小組提供Mastsushita/Panasonic所設計、製作的MNABST-1測試晶片來進行實地環境測試。由測試的結果可以發現,利用本質響應所獲得的結果比實際直接量測的結果至少要好15dB,因此可以證明本質響應抽取技術的穩定性及其優點,除此以外,此技術除可有效、穩定的移除寄生效應及交談失真外,而且不受量測環境雜訊的影響,因此非常的具有實用性。
摘要(英) The methodologies are proposed, designed, and implemented for the removal of the parasitic and crosstalk effects associated with IEEE Std. 1149.4 mixed signal test buses. For this, this thesis defines the intrinsic response and derives the extraction algorithms. The intrinsic response is defined as the response of the circuit being tested by an ideal input signal without the parasitic effects. A deconvolution process is proposed to extract the intrinsic response from the response contaminated by the parasitic effects and crosstalk. The test results using HSPICE simulation data show that the intrinsic responses remain the same regardless of the differences in the parasitic effects, crosstalk, and the variations in the test signals. The proposed methodology is further tested in the real circuit environment using the MNABST-1 test chip designed by Mastsushita/Panasonic and provided by 1149.4 working group.
The test results show that the intrinsic response has an improvement of at least 15 dB as compared to the direct measurement and reassert the claimed advantages. Moreover, the proposed extraction algorithms are robust enough to handle not only the parasitic effects but also the noise in the real measurement environment.
關鍵字(中) ★ 類比測
★ 類比測試匯流排
★ 可測試設計
★ 邊界掃描
★ 本質響應
關鍵字(英) ★ Analog Testing
★ Analog Testability Bus
★ Design for Testability
★ Boundary Scan
★ Intrinsic Response
論文目次 1 introduction
1.1 Background
1.2 Analog Testability Bus
1.3 Analog Test Based on 1149.4
1.4 Thesis overview
2 Survey of Analog Test Methods
2.1 Traditional Methods
2.2 Statistic Fault Model
2.3 Oscillation Test
2.4 Mixed Signal Test Bus
2.4.1 Test Bus Measured Method
2.4.2 The Power Supply Based Method
2.5 Issues of At-Speed Test
2.6 Summary
3 Parasitic Effect Removal in Mixed-Signal Test Buses
3.1 Interconnect Modeling and Circuit Under Test
3.1.1 Testability Bus Modeling
3.1.2 Circuit Under Test
3.2 Intrinsic Response and the Extraction
3.2.1 Intrinsic Response
3.2.2 Intrinsic Response Extraction
3.2.3 Intrinsic Response Test Results
3.3 On Chip Stimulus Test Methodology
3.3.1 On-Chip Test Waveform Generation
3.3.2 Intrinsic Response Extraction
3.3.3 Test Results on SPICE Simulation Data
3.3.4 Test Results on MNABST-1 Based 1149.4 Test Environment
3.4 Off Chip Stimulus Test Methodology
3.4.1 Test Environment
3.4.2 Intrinsic Response Extraction
3.4.3 Parasitic Effect Measuerment
3.4.4 Unit-Gain Buffer Insertion
3.4.5 Simulation Test Results
3.4.6 Experimental Test Results
3.5 Summary
4 Crosstalk Effect Removal in Mixed-Signal Test Buses
4.1 Test Environment and Analog Bus Modeling
4.2 Mathematical Model of The Test Environment
4.3 Crosstalk Removal Methodology
4.4 Simulation Results
4.5 Real Measured Results
4.6 Summary
5 Test Waveform Shaping By Pre-Equalization
5.1 Test Bus Equalization
5.2 Mathematical Inverse Filter
5.3 Simulation Results
5.4 Summary
6 Conclusions
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指導教授 蘇朝琴(Chauchin Su) 審核日期 2000-6-29
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