應用於通訊系統的內嵌式數位訊號處理器架構

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：14

、訪客IP：3.134.76.51

姓名

劉金茂(Jin-Mao Liu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於通訊系統的內嵌式數位訊號處理器架構
(Embedded DSP Core Architecture for Communication Applications)

相關論文

★ 低雜訊輸出緩衝器設計及USB2實體層的傳收器製作	★ 低雜訊輸出緩衝器設計及USB2實體層的時脈回復器製作
★ 應用於數位儲存示波器之100MHz CMOS 寬頻放大器電路設計	★ 具有QAM/VSB模式的載波及時序回復之數位積體電路設計
★ 應用於通訊系統中數位信號處理器之模組設計	★ 應用於藍芽系統之CMOS射頻前端電路設計
★ 具有QAM/VSB 模式之多重組態可適應性等化器的設計與實現	★ 適用於高速通訊系統之可規劃多模式里德所羅門編解碼模組
★ 應用於橢圓曲線密碼系統之低複雜性有限場乘法器設計	★ 適用於通訊系統之內嵌式數位訊號處理器
★ 雷射二極體驅動電路	★ 適用於通訊系統的內嵌式數位信號模組設計
★ 適用在通訊應用之可參數化內嵌式數位信號處理器核心	★ 一個高速╱低複雜度旋轉方法的統一設計架構：角度量化的觀點
★ 5Gbps預先增強器之串列連結傳收機	★ 超取樣技術之資料回復電路設計及其模組產生器

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

今天, 數位訊號處理器(DSP Procesor)是許多通信系統和嵌入的系統的心臟。本論文主要是研究發展一種低價位,可以重複使用,開發時間短,並且可以根據顧客的規格產生數位訊號處理器處理機的架構。
在本論文中,我們根據近幾年所提出有關數位訊號處理器的架構及參數化訊號處理器的設計方法等相關期刊論文,設計出符合我們所要的數位訊號處理器的架構,並且根據我們的需求提出此處理器的定址模式與指令集,並且解決了管線化架構(Pipeline Architecture)
所遭遇的問題。
最後,整顆晶片用Verilog語言描述完成,並且經過Synopsys公司所提供
的數位電路合成工具完成整顆晶片的模擬,本晶片總共使用27915.418 gate counts,並且工作於100MHz的速度。

摘要(英)

Today, DSP processors are at the heart of many communication systems and embedded systems. The object of this thesis is to develop a DSP processor architecture that is suitable to be parameterized by user specification to obtain a DSP processor that has the characteristics of low cost, reusable, and short time-to-market.
In this thesis, we survey several DSP processor architectures and the scheme of parameterized DSP processor core in recent years. Then, we propose a DSP processor architecture that can be parameterized. In addition, we also address the addressing modes in the DSP processor according to the characteristic of DSP algorithm. For high performance DSP processor, we also modify the architecture of MAC unit and design suitable pipeline stages in the processor. We also propose the solutions of pipeline hazard to resolve the pipeline stall.
Finally, the DSP processor is described with Verilog hardware description language and synthesized by Synopsys. From the synthesis reports, the total gate counts are 27915.418 gates and can operate in 100MHz.

關鍵字(中)

★ 數位訊號處理器

關鍵字(英)

★ DSP Processor

論文目次

Contents
1. Introduction
1.1Background and Motivation
1.2Thesis organization
2. Overview and Modification of the DSP Architecture
2.1Introduction
2.1.1 Von Neumann architecture
2.1.2 Harvard architecture
2.1.3 Modified Harvard architecture
2.2 The characteristics of DSP algorithm
2.2.1 The DSP algorithms for communication applications
2.2.2 Using dedicated hardware to implement DSP algorithm
2.3 Parameterized DSP core
2.3.1 The parameters of DSP core
2.3.2 The special functions of DSP core
2.4 Summary
3. Instruction sets and addressing modes
3.1Introduction
3.2Instruction types
3.2.1 TI C54X Instruction sets
3.2.2 Arithmetic and Multiplication instructions
3.2.3 Logic operation instructions
3.2.4 Comparison instructions
3.2.5 Hardware loop instructions
3.2.6 Branching and Subroutine call and return instructions
3.2.7 Special function instructions
3.2.8 Summary
3.3Addressing Modes
3.3.1 Direct addressing mode
3.3.2 Indirect/register addressing mode
3.3.3 Immediate/Absolute addressing mode
3.3.4 Register addressing mode
3.4Summary
4. Pipeline Architecture
4.1Introduction
4.2Pipeline stages
4.2.1 Instruction fetch unit
4.2.2 Instruction decode unit
4.2.3 Operand fetch unit
4.2.4 Execute 1 unit
4.2.5 Execute 2 unit
4.2.6 Write back unit
4.3 Pipeline hazards problem and solutions
4.3.1 Structural hazard
4.3.2 Data hazard
4.3.3 Control hazard
4.5 Summary
5. Design of Data Path Unit
5.1 Introduction
5.2 Overview of the Data Path Function Units
5.3 Multiply-and-Accumulate Unit
5.3.1 Traditional multiply-and-accumulate unit
5.3.2 Modified multiply-and-accumulate unit
5.4 Summary
6. Instruction sets simulation
7. Conclusions

參考文獻

[1] J. Hennessy, D. Patterson, “Computer Organization & Design: The Hardware/Software Interface,” 2 nd edition, Morgan Kaufmann Publishers, 1998.
[2] J. Hennessy, D. Patterson, “Computer Architecture A Quantitative Approach,” 2nd edition, Morgan Kaufmann Publishers, 1996.
[3] V. K. Madisetti, “VLSI Digital Signal Processors: An Introduction to Rapid Prototyping and Design Synthesis,” Butterworth-Heinemann Publishers, 1995.
[4] M. M. Mano, C. R. Kime, “Logic and Computer Design Fundamentals,” Prentice-Hall Publishers, 1997.
[5] V. P. Heuring, H. F. Jordan, “Computer Systems Design and Architecture,” Addison Wesley Longman Publishers, 1997.
[6] P. Lapsley, J. Bier, A. Shoham, E. A. Lee, “DSP Processor Fundamentals,” IEEE
Press, 1997.
[7] “TMS320C54X DSP Reference Set: Volume 1: CPU and Peripherals,” Texas Instruments, 1997.
[8] M. H. Weiss, F. Engel, G. P. Fettweis, “A New Scalable DSP Architecture for System On Chip (SOC) Domains,” IEEE Procs. on ASSP Conf., Vol:4, pp. 1945-1948, March, 1999.
[9] J. Nurmi, J. Takala, “A New Generation of Parameterized and Extensible DSP Cores,” IEEE Workshop Procs. on Signal Processing Systems, pp. 320-329, Nov., 1997.
[10] A. Gierlinger, R. Forsyth, E. Ofner, “Gepard: A Parameterisable DSP Core for ASICS,” ICSPAT, pp. 203-207, 1997.
[11] M. Kuulusa, J. Nurmi, J. Jakala, P. Ojala, H. Herranen, “A Flexible DSP Core for Embedded Systems,” IEEE Design & Test of Computers, Vol. 14, NO. 4, pp.60-68, Oct.-Dec., 1997.
[12] B. W. Kim, J. H. Ynag, C. S. Hwang, Y. S. Kwon, K. M. Lee, I. H. Kim, Y. H. Lee, C. M. Kyung, “MDSP-II: A 16-Bit DSP with Mobile Communication Accelerator,” IEEE Journal of Solid-State Circuits, Vol. 34, NO. 3, pp. 397-404, March, 1999.
[13] I. Verbauwthede, M. Touriguian, “A Low Power DSP Engine for Wireless
Communications,” Journal of VLSI Signal Processing, pp. 177-186, 1998.
[14] E. A. Lee, “Programmable DSP Architectures: Part I,” IEEE ASSP Magazine, pp. 4-19, Oct., 1988.
[15] E. A. Lee, “Programmable DSP Architectures: Part II,” IEEE ASSP Magazine, pp. 4-14, January, 1989.
[16] M. Dolle, M. Schlett, “A Cost-Effective RISC/DSP Microprocessor for Embedded Systems,” IEEE Micro, Vol. 15, NO. 5, pp. 32-40, Oct., 1995.
[17] M. R. Smith, “How RISCy is DSP?,” IEEE Micro, Vol.12, NO. 6, pp. 10-23, DEC. 1992.
[18] M. A. Bayoumi, “VLSI Architectures for DSP Applications: Current Trends,” IEEE Procs. on Circuits and Systems, Vol. 1, pp. 150-153, Aug., 1992.
[19] B. Lin, S. Vercauteren, H. D. Man, “Embedded Architecture Co-Synthesis and System Integration,” IEEE Procs. on Hardware/Software Co-Design, pp. 2-9, March, 1996.
[20] R. E. Owen, D. Martin, “A Uniform Analysis Method for DSP architectures and Instruction Sets with A Comprehensive Example,” IEEE Workshop Procs. on Signal Processing Systems, pp.528-537, Oct., 1998.
[21] P. Blinzer, E. Cochlovius, M. Schafers, K-P. Wachsmann, “VLSI Chip Design with the Hardware Description Language VERILOG: Aintroduction Based on A Large RISC Processor Design,” Springer Publishers, 1996.
[22] H. H. Wang, “Module Design of DSP Core for Communication System,” Dep. Elec. Eng., National Central University, Taiwan, June, 2000.
[23] M. Alidina, G. Burns, C. Holmqvist, E. Morgan, D. Rhodes, S. Simanapalli, M. Thierbach, “DSP 16000: A High Performance, Low Power Dual-MAC DSP Core for Communications Applications,” IEEE Procs on Custom Integrated Circuits Conference, pp. 119-122, May, 1998.
[24] R. Y. Yen, “Implementation of Carrier Recovery and Timing Recovery for QAM/VSB mode CATV System,” Dep. Elec. Eng., National Central University, Taiwan, June, 1999.
[25] S. Lin, D. J. Costello, “Error Control Coding: Fundamentals and Applications,” Prentice-Hall Publishers, 1983.
[26] J. C. Huck, M. J. Flynn, “Analyzing Computer Architectures,” IEEE Press, 1989.
[27] K. Hwang, “Computer Architecture: Principles, Architecture, and Design,” 1979.

指導教授

周世傑(Shyh-Jye Jou)

審核日期

2000-7-14

推文