博碩士論文 87324002 詳細資訊




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姓名 莊家碩(Jia-Soy Chuang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用於藍芽系統之CMOS射頻前端電路設計
(RF CMOS Front-End Circuit Design for Bluetooth Receiver)
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摘要(中) 在本論文中, 以應用於藍芽無線接收系統的來探討射頻前級的整合性,並且針對系統規格提出適用於藍芽系統之低中頻接收機,所有的線路包含有低雜訊放大器,混波器,鏡相消除濾波器, 及正交信號產生器, 模擬上顯示鏡相消除為30dB,
雜訊指數為15.2dB, 敏感度-70.8dBm, 電壓增益35.8dB, 三階信號交會點-14dBm. 使用3.3V的電壓, 及台灣積體電路公司所提供 0.6微米 SPTM 金氧半場效應電晶體, 功率消耗為250mW, 面積是3000微米4000微米.
摘要(英) Since the rapid development of the CMOS technology, a RF analog front-end receiver can be integrated on a single chip. This thesis introduces a highly integrated RF receiver front end for Bluetooth system. This front-end design composed of low noise amplifier, two downconversion mixers, passive polyphase with buffers, and active polyphase filter. It receives the 2.4GHz desired high frequency signal ,and then translates it to 700KHz. Besides downconversion, it also needs image rejection by active polyphase filter. At last, it generates I_Q path and feed I_Q to baseband. Before I_Q fed into baseband, it needs AGC to reduce the dynamic range (44dB) and SAW filter as channel select filter. The design of AGC is not included in the thesis.
The whole analog front-end is implemented by using TSMC 0.6um SPTM standard CMOS technology under 3.3V power supply. It has 35.8dB cascaded gain, 15.2dB noise figure, 24dB image rejection ratio, -14dBm IIP3. The total RF front-end power consumption is about 250mW. The total chip area is .
關鍵字(中) ★ 藍芽
★ 射頻電路
關鍵字(英) ★ Bluetooth
★ RF Circuit
論文目次 Contents
1. Introduction 3
1.1 Motivations……………………………….. 3
1.2 Thesis Organization………………………. 4
2. Receiver Architectures Overview 5
2.1 Introduction………………………………... 5
2.2 General Considerations……………………. 6
2.3 Heterodyne Receiver………………………. 8
2.4 Homodyne Receiver………………………. 10
2.5 Image-Reject Receiver…………………….. 13
2.5.1 Hartley architecture …………………….. 13
2.5.2 Weaver architecture…………………….. 15
2.6 Wideband-IF Receiver…………………….. 16
2.7 Low-IF Receiver ………………………….. 17
2.8 Summary ………………………………….. 19
3.Bluetooth Architecture 21
3.1 Introduction ………………………………. 21
3.2 Specifications …………………………….. 22
3.3 Active Polyphase Receiver ………………. 24
3.3.1 Complex signal domain ………………. 24
3.3.2 Real signal domain …………………. 27
3.4 Macros specifications ……………………. 30
3.5 Summary ………………………………… 31
4.Low Noise Amplifier 33
4.1 Introduction ………………………………. 33
4.2 Integrated Inductors Realization …………. 33
4.3 Noise Figure ……………………………… 37
4.4 Circuit Design and Simulation Results …….. 39
4.5 Physical Layout …………………………….. 47
4.6 Summary …………………………………… 48
5.Mixer 49
5.1 Introduction ………………………………… 49
5.2 Circuit Design and Simulation Results …….. 49
5.2.1 Conversion gain ………………………… 51
5.2.2 Noise figure …………………………….. 51
5.2.3 Simulation results …………………….. 52
5.3 Physical Layout …………………………….. 53
5.4 Summary …………………………………… 55
6.Quadrature Generator 56
6.1 Introduction ……………………………….. 56
6.2 Polyphase Network ……………………….. 56
6.3 Buffer ……………………………………... 58
6.4 Physical Layout …………………………… 59
6.5 Summary ………………………………….. 60
7.Active Polyphase Filter 61
7.1 Introduction ………………………………... 61
7.2 Dou.ble-MOSFET Resistor ………………… 61
7.3 Operational Amplifier ……………………… 63
7.4 6th order Butterworth Filter ………………… 65
7.5 Physical Layout ……………………………. 68
7.6 Summary …………………………………… 70
8.Conclusions 71
Appendix 72
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指導教授 周世傑(Shyh-Jye Jou) 審核日期 2000-7-18
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