博碩士論文 87324004 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:9 、訪客IP:3.230.154.129
姓名 林欣怡(Hsin-Yi Lin)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 具有QAM/VSB模式的載波及時序回復之數位積體電路設計
(Implementation of the QAM/VSB dual mode Carrier Recovery and Timing Recovery)
相關論文
★ 低雜訊輸出緩衝器設計及USB2實體層的傳收器製作★ 低雜訊輸出緩衝器設計及USB2實體層的時脈回復器製作
★ 應用於通訊系統的內嵌式數位訊號處理器架構★ 應用於數位儲存示波器之100MHz CMOS 寬頻放大器電路設計
★ 應用於通訊系統中數位信號處理器之模組設計★ 應用於藍芽系統之CMOS射頻前端電路設計
★ 具有QAM/VSB 模式之多重組態可適應性等化器的設計與實現★ 適用於高速通訊系統之可規劃多模式里德所羅門編解碼模組
★ 應用於橢圓曲線密碼系統之低複雜性有限場乘法器設計★ 適用於通訊系統之內嵌式數位訊號處理器
★ 雷射二極體驅動電路★ 適用於通訊系統的內嵌式數位信號模組設計
★ 適用在通訊應用之可參數化內嵌式數位信號處理器核心★ 一個高速╱低複雜度旋轉方法的統一設計架構:角度量化的觀點
★ 5Gbps預先增強器之串列連結傳收機★ 超取樣技術之資料回復電路設計及其模組產生器
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 在本篇論文中,我們提出一個可應用於有線電視上的載波及時序回復電路架構 : 不只適用於垂直正交振幅調變 (QAM, Quadrature Amplitude Modulation),同時也適用於殘旁邊帶振幅調變 (VSB, Vestigial Sideband Modulation),並且以很少的硬體代價實現之。在載波回復電路中,我們以驟斜率方法 (Steep Gradient Method) 來實現電路所需的相位檢測器 (Phase Detector) ;而在時序回復電路中,我們則使用鮑率 (Baud-Rate) 相位檢測器。此外,為了簡化電路的實現,我們另外採用了方向理論 (Sign Algorithm),使得原來電路中的乘法器可以用二補數電路來取代。為了增加載波回復電路的頻率追蹤範圍 (Acquisition Range),在垂直正交振幅調變模式中,我們加入了一對相位解旋/旋轉電路 (Derotator/Rotator Pair) 於載波回復電路之前;而在殘旁邊帶振幅調變模式中,我們另外加入一個鎖頻迴路 (Frequency Locked Loop)。另外,我們還利用纜線通道模型(Cable Channel Models)來模擬有線電視纜線的傳輸效應。為了使載波回復電路能抵抗纜線的傳輸雜訊,在殘旁邊帶振幅調變模式中,我們重新調整鎖頻迴路的參數值以改善穩態時的誤差;在垂直正交振幅調變模式中,我們則採用切換載波回復路徑的方式來解決等化器箝制載波回復電路的頻率追蹤範圍的問題。如此,依據C語言所架構的系統模擬結果,載波回復電路具有±100KHz的頻率追蹤範圍。最後,我們將鎖頻迴路、載波回復電路、時序回復電路、數值控制震盪器(NCO, Numerically Controlled Oscillator) 以及混波器 (Mixer) 以硬體描述語言Verilog來描述,並以Synopsys做電路的整合與最佳化。根據整合後的結果顯示,整個電路總共需要24,531閘。
摘要(英) The proposed CR adopts a Steep Gradient mothod, while the proposed TR em-ploys a baud-rate TR in our system. To reduce the hardware complexity, both of them use sign algorithm.
Furthermore, to increase the acquisition range of CR, a Frequency Locked Loop (FLL) is used in VSB mode, while a derotator/rotator pair is adopted in QAM mode. As a result, the CR can reach ±100KHz acquisition range from simulation results when using the ideal-like channel model with a little intersymbol interference (ISI).
Besides, for enhancing the CR to fit all the feasible cable channel models, the filter of the FLL was re-designed in VSB mode. The filter coefficients have been modified that deamativally reduce the hardware complexity.
Moreover, the control of rotator/de-rotator to switch the CR loop during different stages are used to enhance the performance of the CR and the EQ in QAM mode.
Finally, the whole design, which consists of a mixer, a FLL, a CR, a TR, a loop controller and two NCOs, is desribed with Verilog hardware language and synthesized by Synopsys. From synthesis reports, the total gate counts are 24,531 gates.
關鍵字(中) ★ 纜線電視
★ 載波回復
★ 頻率鎖相迴路
★ 時序回復
★ 殘邊帶調變
★ 垂直正交振幅調變
關鍵字(英) ★ CATV
★ Carrier Recovery
★ Frequency Locp Loop
★ Timing Recovery
★ Vestigial Sideband Modulation
★ VSB
★ Quadrature Amplitude Modulation
★ QAM
論文目次 1Introduction
1.1Motivation
1.2Thesis Organization
2Overview of the CATV Transceiver
2.1Transmitter
2.2Channel Model
2.3Receiver
2.3.1 VSB Mode Operation
2.3.2 QAM Mode Operation
2.4Summary
3Frequency Locked Loop
3.1Introduction
3.1.1 Frequency Detector Theorem
3.1.2 Loop Filter of FLL
3.2Enhancement and Simulation Results
3.2.1 Filter Design
3.3Hardware Implementation
3.3.1 IIR Filter Design
3.3.2 Multiplier Design
3.3.3 Synthesis Results
4Carrier Recovery Loop
4.1Introduction of Carrier Recovery
4.1.1 Introduction of PLL
4.1.2 Phase Detector Theorem
4.1.3 De-rotator / Rotator Pairs
4.2Enhancement and Simulation Results
4.2.1 Bandwidth Adjustment
4.3Hardware Implementation
4.3.1 Phase Detector
4.3.2 Pre-filter and Bandwidth Controller
4.3.3 PI-filter
4.3.4 Synthesis Results
5Timing Recovery
5.1Architecture of Timing Recovery
5.2Simulation Results
5.3Hardware Implementation
6Overall Hardware Implementation
6.1Overall Circuit Design
6.1.1Loop Controller
6.1.2NCO
6.2Design Flow
6.3Testing Consideration
6.4Chip Summary
7Conclusions
參考文獻 [1] M. T. Shiue, "Transceiver VLSI Design for High Speed Local Access Modems," PH. D. Thesis, National Central University, 1998.
[2] R. E. Best, Phase-Locked Loops: Theory, Design, and Applications, 2nd edition, New York, McGraw-Hill, 1993.
[3] E. A. Lee, D. G. Messerschmitt, Digital Communication, 2nd edition, Boston: Kluwer, 1994.
[4] K. H. Mueller, M Mueller, “ Timing Recovery in Digital Synchronous Data Receivers,” IEEE Transactions Communication, Vol Com 24, No.5 May 1976.
[5] G. H. Kuo, "VLSI Implementation of Timing Recovery and Carrier Recovery for QAM/VSB Dual mode CATV System," Master Thesis, National Central University, 1998.
[6] M. Chelehmal, "Transmission of Digital HDTV Part 2," Communication Technology, pp. 47-52, Dec. 1992.
[7] D. T. Gall, "Digital Modulation on Coaxial/Fiber Hybrid Systems," Communication Technology, pp.42-45, Jun. 1995.
[8] F. Van der Putten, M. Trevisan, L. Rysdale, and C. Peterson, "Lower Layer Protocols and Physical Interfaces," DAVIC 1.0 Specifications, Part8, Revision 3.0, May 1995.
[9] R. Y. Yen, "Implementation of Carrier Recovery and Timing Recovery for QAM/VSB mode CATV System," Master Thesis, National Central University, 1999.
[10] M. T. Shiue, C. K. Wang, K. H. Huang, and C. I. Huang, "A Dual Mode Digital Transceiver for Both the QAM and VSB Digital Communication System," Taiwan, R.O.C. patent 1998, and U.S.A Patent filed in 1997.
[11] M. T. Shiue, K. H. Huang, C. K. Wang, and Winston I. Way, "A VLSI Architecture Design for Both QAM and VSB Digital CATV Transceiver," TJCOM98, Hsin-Chu, Taiwan, R.O.C., Jan. pp. 20-22, 1998.
[12] A. Cook and J. Stern, "Optical Fiber Access - Perspectives toward the 21st Century," IEEE Commun. Mag., vol. 31, NO. 2, pp. 78-86, Feb. 1994.
[13] D. G. Messerschmitt, "Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery," IEEE Trans. Commun., Vol. 27, pp. 1288-1295, Sept. 1979.
[14] H. Sari and S. Moridi, "New Phase and Frequency Detectors for Carrier Recovery in PSK and QAM Systems," IEEE Trans. Commun., Vol. 36, pp. 1035-1043, Sept. 1988.
[15] F. M. Gardner, "Frequency Detectors for Digital Demodulators via Maximum-likelihood Derivation," ESA Final Report: Part II, ESTEC Contract no. 8022/88/NL/DG, June 1990.
[16] F. M. Gardner, "Properties of Frequency Difference Detectors," IEEE Trans. Commun., Vol. 33, pp. 131-138, Feb. 1985.
[17] A. N. D'Andrea and U. Mengali, "Design of Quadricorrelators for Automatic Frequency Control Systems," IEEE Trans. Commun., Vol. 41, pp. 988-997, June 1993.
[18] T. Alberty and V. Hespel, "A New Pattern Jitter Free Frequency Error Detector," IEEE Trans. Commun., Vol. 37, pp. 159-163, Feb. 1989.
[19] C. R. Cahn, "Improving Frequency Acquisition of a Costas Loop," IEEE Trans. Commun., vol. COM-25, pp. 1453-1459, Dec 1977.
[20] A. V. Oppenheim and R. W. Schafer, Discrete-time Signal Processing, Prentice Hall, 1989.
[21] W. C. Lindsey and M. K. Simon, Telecommunications System Engineering, Englewood Fliffs: Prentice-Hall, 1973.
[22] D. Y. Hsin “Design and Implementation of Multi-states adaptive equalizer with QAM/VSB mode,” Master Thesis, National Central University, 1999.
[23] A. Yamagishi, M. Ishikawa, T. Tsukahara, S. Date, "A 2-V, 2-GHz Low-Power Direct Digital Frequency Synthesizer Chip Set for Wireless Communication," IEEE Custom Integrated Circuits Conf., pp. 319-322, 1995.
[24] I. C. Yung, "Numerical Controlled Oscillator Using TSPC," Master Thesis, National Central University, 1995.
[25] H. T. Nicholas, III, and H. Samueli, "A 150-MHz direct Digital Frequency Synthesizer in 1.25-um CMOS with -90-dBc Spurious Performance," IEEE Journal of Solid-State Circuits, vol.26, no.12, pp.1959-1969, Dec. 1991.
指導教授 周世傑(Shyh-Jye Jou) 審核日期 2000-7-17
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明