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姓名 王惠萱(Hui-Hsuan Wang) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 應用於通訊系統中數位信號處理器之模組設計
(Module Design of DSP Core for Communication System)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 在本篇論文中，我們提出一些應用於通訊系統中內嵌式數位信號處理器(Digital Signal Processor)之模組設計。 我們也提出一適用於此一內嵌式特性之輸入輸出(I/O)設計，此輸入輸出處理之資料包括程式碼及外部資料之輸入，其操作模式包含主機操作模式(Host Port Interface)、平行操作模式(Parallel)及即時資料操作模式(Real time)。
在資料通路(Data path)上，我們也提供 40 位元之算數邏輯運算單元及具有左移15右移16位之位移器和有限脈衝頻率響應(Finite Impulse Response, FIR)。 除此之外我們也提供一些另外的選擇，如通訊上常用之特殊運算單元如Hamming 距離之計算及多層切片器(Slicer) ，以上所提之法雖可用軟體方法實現但在系統速度要求越來越高之時會有不敷使用之憾，所以提供特殊應用指令之硬體實現之模組實為未來高速DSP之趨勢。 在FIR 的應用中我們亦提出一可縮減位元長度式乘法器，此一概念應用在陣列式乘法器上可有效降低面積48%，並拓展此法至Booth乘法器之加法列，其訊雜比(SNR)亦比多取一位元之加法列高出3dB而且面積省了10%。
最後，本篇論文亦提供模組設計流程其中包括: ALU，位移器，Slicer 及Hamming 距離計算器。 而且這些模組產生器所產生之Verilog皆為可被合成之程式碼。摘要(英) In this thesis, the some modules used in the programmable DSP embedded core for communication system are proposed. The proposed I/O function combines the data and program source that include Host-Port-Interface (HPI), parallel and Real-time mode. In the data-path of our DSP, we develop the 40-bits ALU and 40-bits Barrel-shifter with shift +15 to -16. Besides, we also provide the optional hardware functions. Such as Hamming-Distance-Calculator, Multi-Level-Slicer and FIR filter. The Hamming-Distance-Calculator can calculate the minimum distance of two 16-bits input data in 5.22 ns. In some communication application, we usually need the variable slicer-level to help the system increase the performance. About the optional FIR function, we will propose a new reduced-width multiplier that can replace the multiplier in conventional filter and save 48% area in each multiplier of the FIR filter.
In this thesis, we also provide module generator for ALU, Barrel-shifter Multi-Level-Slicer and Hamming-Distance-Calculator and these generators generate the synthesizable Verilog code.關鍵字(中) ★ 數位信號處理器
★ 模組設計
★ 可參數化關鍵字(英) ★ Digital Signal Processor
★ Module design
★ Parameter論文目次 1 Introduction ………………………………………………………………01
1.1 Motivation…………………………………………………………… 01
1.2 Thesis Organization…………………………………………………… 04
2 Instruction Sets and Structure………………..………………………………05
2.1 TI TMSC54X DSP Instruction Sets _ALU and Shifter…………………05
2.1.1 Basic Instruction Sets ………….………………………………….05
2.1.2 Special Instruction Sets…………………………………………….06
2.2 NCU_C54x_2000 Process instruction sets _ALU and Shifter ………….06
2.2.1 Basic Instruction Sets ….....………………………………………07
2.2.2 Special Instruction Sets ……..………………………………….08
2.3 The architecture of NCU_C54x_2000 DSP Processor ……….……….09
2.3.1 Bus Structure ………………..………………………………….10
2.3.2 Characteristic of Function Units …………………………………11
2.4 Summary ………………………………………….…..…………13
3 Design of I/O and Data path ……………………………………………..14
3.1 Input _ Output Design …………………………………………….14
3.1.1 Design of the I/O Function .………………………………….15
3.1.2 Synthesis and Simulation Results …………………………….19
3.2 Basic Data Path Design _ ALU and Shifter……………………….21
3.2.1 Design of the ALU and Barrel_Shifter Function……………….21
3.2.2 Synthesis and Simulation Results….………………………….25
3.3 Special Function Design……..………….………………………….27
3.3.1 Design of the Hamming_Distance_Calculation
and Slicer Function ………………………………………….27
3.3.2 Synthesis and Simulation Results ...……………………………29
4 Reduced-Width Multipliers in Digital Signal Process …………………….32
4.1 Conventional Reduced Width Multiplier………………………34
4.1.1 Post-Truncation Method……………….………….. 34
4.1.2 Pre-Truncation Method ……………………….……35
4.1.3 Fixed Value Compensation Multiplier………..…… .35
4.2 New Array Multiplier With Compensation Vector …….…….36
4.3 Reduced-Width Booth Multiplier with Compensation Vector…45
4.3.1 Drive New Compensation Vector .………………….. 47
4.3.2 Low-Error Reduced-Width Booth Multiplier …...….. 51
4.4 Summary
5 Module Design of Parameterized ALU, Barrel Shifter,
Hamming Distance Calculator and Slicer .………………………54
5.1 Module Generation of Basic Function Units ………….……... 54
5.2 Module Design of Special Function Units .……………………56
6 Conclusions …………………………………………………….. 61
Reference…………………………………………………………... 63
Appendix A The TI C54x Instruction Sets and Description……………A.1
Appendix B The Descriptions of HPIA, HPID and HPIC……………..B.1參考文獻 [1] J. Bartholomew, A. Jurecska, "A Multi-Level Co-simulation Environment for Embedded DSP System Design," DSP Conference-Deutshland 1999 Synopsys, Inc, July 1999.
[2] B. W. Kim, J. H. Yang, C. S. Hwang, Y. S. Kwon., K. M. Lee., I. H. Kim., Y. H. Lee., C. M. Kyung "MDSP-II: a 16-bit DSP with mobile communication accelerator ," Solid-State Circuits, IEEE Journal of Volume: 34 3 , March 1999 , Page(s): 397 - 404
[3] E. A. Lee, "Programmable DSP's:A brief overview," IEEE Micro Mag., vol. 10, no. 5, Otcober 1990 ,Page(s):14 - 16
[4] J. M. Liu, "Embedded DSP Core Architecture for Communication System," Dep. Elec. Eng., National Central University, Taiwan, June,2000
[5] TMS320C54x DSP Reference Set Volume 1: CPU and Peripherals
[6] M. Dolle, S. Jhand, W. Lehner, O. Muller, M. Schlett, " A 32-b RISC/DSP microprocessor with reduced complexity " in Solid-State Circuits, IEEE Journal of Volume: 32 7 , July 1997 , Page(s): 1056 -1066
[7] P. Denyer, "DSP processor fundamentals, architectures and features, " Berkeley Design Technology, 1996
[8] E. A. Lee, "Programmable DSP Architectures: Part I," IEEE ASSP Magazine , October 1988 ,Page(s):4 - 19
[9] M. M. Mano, C. R. Kime, "Logic And Computer Design Fundamentals," Pretice-Hall International, Inc.
[10] W. Lee, P. E. Landman, B. Barton, S. Abiko, H. Takahashi, H. Mizuno, S. Muramatsu, K. Tashiro, M. Fusumada, L. Pham, F. B., E. Ego, G Gallo, H. Tran, C. Lemonds, A. Shih, M. Nandakumar, R.H Eklund, I. C. Chen, "A 1-V programmable DSP for wireless communications [CMOS] ," Solid-State Circuits, IEEE Journal of Volume: 32 11 , Nov. 1997 , Page(s): 1766 -1776
[11] TMS320LC549 Fixed-Point Digital Signal Processor Advance Infotmation, Revision 1.6 , JUNE 1997
[12] TMS320C548/9 Boot Loader and On-Chip ROM Description Technical Reference, 1997
[13] The TMS320C54c DSP HPI and PC parallel Port Interface Application Report, 1997
[14] S. S. Kidambi, F. El-Guibaly, A. Antoniou, "Area-efficient multipliers for digital signal processing applications," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 43, No. 2, Feb. 1996, Page(s): 90 - 95
[15] J. M. Jou, S. R. Kuang, "Design of low-error fixed-width multipliers for DSP applications," Electronics Letters, Vol.33 No.19, Sept. 1997, Page(s):1597-1598
[16] J. M. Jou, S. R. Kuang, R.D. Chen, "Design of low-error fixed-width multipliers for DSP applications," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Volume 46, No.6, June 1999, Page(s):836 -842
[17] N. Mukherjee, J. Rajski and J. Tyszer, "Design of testable multipliers for fixed-width data paths," IEEE Trans. On Computer, Vol.46, No.7, July 1997, Page(s):.795-810
[18] K. Huang, , Computer arithmetic-principles, architecture and design, John Wiley & Sons, Inc.,1979
[19] T. S. Yokohama., Patent Name: MILTIPLYING CIRCUIT,
Patent Number: US4,598,382
[20] D.C. Montgomery, E.A Peak, Introduction to Linear Regression Analysis, John Wiley & Sons. Inc., 1982
[21] J. H. Yang., B. W. Kim., S. J. Nam., Y. S. Kwon., D. H. Lee., J. Y. Lee., C. S. Hwang., Y. H. Lee, C. M. Kyung., "MetaCore: An Application-Specific Programmable DSP Development System," IEEE Transactions on VLSI Systems, Vol.8 No.2, April 2000, Page(s):173 -183
[22] R. Woudsma , PICS, "a flexible approach to embedded DSP cores," in Proc. Int. Conf. Signal Processing Applications and Tech-nology (ICSPAT), Oct. 1994
[23] J. Sato, A. Y. Alomary, M. Imai., "EAS-I: A hardware/software co-design system for ASIP development," IEICE Trans. Fundamentals, vol. E77-A, no. 3, Mar. 1994 , Page(s): 483 - 491
[24] J. Sato, M. Imai, and N. Hikichi, "An integrated design environment for application specific integrated processor," in Proc. Int. Conf. Computer Design, 1991
[25] B. Liu, S. Vercantern, H.D. Man, "Embedded Architecture Co-synthesis and System Intergration," IEEE Procs. On Hardware/Software Co-design, Page(s): 2 - 9, March, 1996.指導教授 周世傑(Shyh-Jye Jou) 審核日期 2000-7-17 推文 plurk
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