博碩士論文 87324006 詳細資訊


姓名 郭淑華(Shu-Hua Kuo)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 低雜訊輸出緩衝器設計及USB2實體層的傳收器製作
(The Low Noise Output Buffer Design Techniques and Transceiver Implementation for USB2 Physical Layer)
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摘要(中) 高速I/O是決定電子裝置間能否成功傳送資料的重要因素。而同時性邏輯轉換雜訊(Simultaneous Switching Noise)又是高速數位電路中最主要的雜訊之一。所以在本論文中,首先我們先對同時性邏輯轉換雜訊做一概略性的介紹。接下來提出一個不但可以降低同時性邏輯轉換雜訊與電路輸出振盪問題而且還能維持驅動能力的AC/DC輸出緩衝器。並將以UMC 0.35um 1P5M的數位製程,來實際驗證理論分析及輸出級電路設計技巧。經由晶片量測的結果,我們在電路輸出震盪及同時性邏輯轉換雜訊上可以分別降低60%及40%。另外,我們也提出了一套特性化流程來估算SSO(Simultaneous Switching Outputs)所需的電源/接地對的個數及其所額外增加的延遲時間。
近來,萬用串列匯流排(Universal Serial Bus, USB)已經成為個人電腦平台中相當重要的一部份。USB能允許多種週邊裝置同時接上並且即插即用。因此在此篇論文中,我們設計了一個應用於此USB系統高速模式480Mb/s頻寬的傳收器,而此USB實體層系統中包含了一個傳收器(Transceiver),兩個封包檢出器(Envelope Detector)及一個時脈回復器(Clock Recovery)。
摘要(英) High-speed I/O is the key component to successfully transmit data between electronic devices. Simultaneous switching noise (SSN) or called ground bounce is one of the major noise sources in high-speed digital circuit. There are two research topics in this thesis. First we focus on the overview of SSN. We will propose an output buffer - AC/DC for reducing SSN, output signal ringing and maintain DC current capability. The test chip by using UMC 0.35um 1P5M digital process will be implemented to verify the theoretical analysis results and circuit design techniques. For example, SSO improvement from 3 to 11 for the YC2/ACDC2 cases, considering the Quiet VDD case. Measurement results show that our invention can reduce the output ringing by 60%, and VDD/GND line bounce by 40% when comparing with conventional buffers used in standard commercial cell library with 2ns rise/fall time and 40pF output loading capability. Also we propose a characterization procedure to estimate power pads for simultaneous switching outputs (SSO).
The Universal Serial Bus (USB) technology is now becoming an integral part of the personal computer platform. USB is one of the first I/O ports where several types of devices can be connected simultaneously. Thus, in the second research topic, the transceiver architecture and circuit is proposed for USB2 high-speed mode with 480Mb/s bandwidth. The physical layer of USB2 consists of transceiver, two envelope detector, and clock recovery.
關鍵字(中) ★ 同時性轉換雜訊
★ 接地反彈
★ 萬用串列匯流排
★ 同時性轉換輸出緩衝器
關鍵字(英) ★ SSN
★ Ground bounce
★ USB
★ SSO
論文目次 Contents
Abstract…………………………………………………………………i
Acknowledgements…………………………………………………ii
Contents………………………………………………………………iii
List of Figures………………………………………………………vii
List of Tables……………………………………………………………xi
1 Introduction……………………………………………………………………...1
1.1 Motivation………………………………………………………………….1
1.2 Thesis Organization……………………………………………………….3
2 Low Noise Output Buffer Design Techniques……………………………...4
2.1 Introduction……………………………………………………………..….4
2.2 The Analysis of Simultaneous Switching Noise and Simultaneous Switching Outputs…5
2.3 Summary of SSN reduction guideline…………………………………10
2.4 Overview of Simultaneous Switching Noise Reduction Techniques..11
2.4.1 Weighted and Distributed Method……………………………11
2.4.2 Low Bouncing Output Driver Method………………………12
2.4.3 CMOS Output Buffer with Reduced L-di/dt Noise…………13
2.4.4 Ground Bounce Isolated Output Buffer………………………15
2.5 Proposed Low Noise Output Buffer Design Techniques……………16
2.5.1 Design Techniques to reduce SSN and Output Ringing……17
2.5.2 Basic Operation…………………………………………………18
2.5.3 Simulation Results………………………………………………22
2.6 Summary…………………………………………………………………32
3 Characterization of Simultaneous Switching Outputs…………………33
3.1 Introduction……………………………………………………………....33
3.1.1 SSO Classification and Definition……………………………33
3.1.2 Static and Dynamic SSN Margin………………………………35
3.1.3 Simulation model for SSO………………………………………36
3.2 Characterization of Simultaneous Switching Outputs………………38
3.2.1 The Procedure of SSOP/SSOG Estimation……………………38
3.2.2 A Design Example of SSOG Characterization…………………40
3.3 Characterization of TSSO (Excess Incremental Delay) ………………42
3.3.1 The Procedure of TSSO Estimation………………………………43
3.3.2 A Design Example of TSSO Characterization…………………43
4 Test Chip Implementation and Measurement Results…………………46
4.1 Test Key for AC/DC Output Buffer…………………………………46
4.1.1 Testing Consideration…………………………………………47
4.1.2 Layout Implementation…………………………………………48
4.2 Measurement Results……………………………………………………51
4.3 Chip Summary……………………………………………………………63
5 Overview of USB2 Specifications…………………………………………65
5.1 Introduction………………………………………………………………65
5.2 Architecture Overview of USB2…......................................................66
5.2.1 USB2 System Description……..................................................66
5.2.2 USB2 Physical Interface…….........................................................67
5.2.3 USB2 Data Flow Type....................................................................68
5.2.4 USB2 Bus Protocol..........................................................................68
5.3 Overview of USB2 Transceiver.................................................................69
5.4 Specification of USB2 clock recovery.......................................................69
5.5 Summary......................................................................................................71
6 USB2 Transceiver Implementation………………………………………72
6.1 Introduction………………………………………………………………72
6.2 The Architecture of Transceiver for USB2……………………………75
6.3 The Circuit Design of Transmitter………………………………………76
6.3.1 Parallel Input Serial Output Circuit……………………………77
6.3.2 Driver and Current Source………………………………………79
6.3.3 Voltage Reference Circuit………………………………………80
6.3.4 Disconnection Envelop Detector………………………………81
6.4 The Circuit Design of Receiver………………………………………….83
6.4.1 Level Shifter and Differential to Single Circuit………………85
6.4.2 Transmission Envelop Detector…………………………………86
6.5 Summary…………………………………………………………………88
7 Conclusions……………………………………………………………………93
Bibliography………………………………………………………………………94
參考文獻 Bibliography
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[21] R. Senthinathan and J. L. Prince, "Application Specific CMOS Output Driver Circuit Design Techniques to Reduce Simultaneous Switching Noise," IEEE J. Solid-State Circuits, vol.28, No.12, pp.1383-1388, Dec. 1993.
指導教授 周世傑(Shyh-Jye Jou) 審核日期 2000-6-12
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