低雜訊輸出緩衝器設計及USB2實體層的時脈回復器製作

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姓名

邱瑞德(Ran-De Cho) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

低雜訊輸出緩衝器設計及USB2實體層的時脈回復器製作

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摘要(中)

其次我們提出一個新的全數位式時脈回復器的架構，並利用USB2的高速規格(480Mb/s)來驗證。USB2為一個新的電腦週邊萬用匯流排的規格，而USB2中的實體層製作主要包涵了接發端和時脈回復器，製作一個全數位式、低功率損耗和小面積時脈回復器是USB2中相當重要的一環。而我們除了提出這個時脈回復器之外，同時也提出了整個USB2實體層的製作架構。

摘要(英)

Second, a clock recovery architecture and circuit is proposed for Universal Serial Bus 2 (USB2) high-speed mode (480M bits per second). USB2 is a new serial bus standard for the peripheral of PC today. The physical layer of USB2 consists of a transceiver and the clock recovery (CR). For USB2 high-speed 480M bits per second, it is important to design an all digital, low power, small area clock recovery. In this thesis, we propose an overall architecture of USB2 physical layer. We also propose a new all digital clock recovery for USB2 physical layer. However, it consume only when working at 480M bit per second.

關鍵字(中)

★ 低雜訊
★ 輸出緩衝器
★ 時脈回復器
★ 同時性邏輯轉換雜訊

關鍵字(英)

★ usb2
★ output buffer
★ clock recovery
★ Simultaneous Switching Noise

論文目次

Contents
CHAPTER 1
INTRODUCTION1
1.1 LOW NOISE OUTPUT BUFFER DEAIGN TECHNIQUES1
1.2 CLOCK RECOVERY FOR USB2 PHYSICAL LAYER2
1.3 THESIS ORGANIZATION2
CHAPTER 2
LOW NOISE OUTPUT BUFFER DESIGN TECHNIQUES4
2.1 INTRODUCTION4
2.2 THE ANALYSIS OF SIMULTANEOUS SWITCHING NOISE AND SIMULTANEOUS SWITCHING OUTPUTS5
2.3 SUMMARY OF SSN REDUNCTION GUIDELINE10
2.4 SIMULTANEOUS SWITCHING NOISE REDUCTION TECHNIQUES11
2.4.1 WEIGHTED AND DISTRIBUTED METHOD11
2.4.2 LOW BOUNCING OUTPUT DRIVER METHOD12
2.4.3 CMOS OUTPUT BUFFER WITH REDUCED L-DI/DT NOISE14
2.4.4 GROUND BOUNCE ISOLATED OUTPUT BUFFER14
2.5 ADAPTIVELY SEPARATED SSN DESIGN TECHNIQUES16
2.5.1 ARCHITECTURE DESIGN OF ADAPATIVELY SEPARATED SSN BUFFER17
2.5.2 CIRCUIT DESIGN OF ADAPTIVELY SEPARATED SSN BUFFER17
2.5.3 SIMULATION RESULTS22
2.6 SUMMARY27
CHAPTER 3
SIMULTANEOUS SWITCHING OUTPUTS CHARACTERIZATION28
3.1 INTRODUCTION28
3.1.1 SSO CLASSIFICATION AND DEFINITION28
3.1.2 STATIC AND DYNAMIC SSN MARGIN30
3.1.3 SIMULATION MODEL FOR SSO31
3.2 SIMULTANEOUS SWITCHING OUTPUTS CHARACTERIZATION33
3.2.1 THE PROCEDURE OF SSOP/SSOG ESTIMATION33
3.2.2 A DESIGN EXAMPLE OF SSOG CHARACTERIZATION35
3.3 EXCESS INCREMENTAL DELAY CHARACTERIZATION37
3.3.1 THE PROCEDURE OF TSSO ESTIMATION38
3.3.2 A DESIGN EXAMPLE OF TSSO CHARACTERIZATION38
CHAPTER 4
LOW NOISE OUTPUT BUFFER CHIP IMPLEMENTATION AND MEASURED RESULTS41
4.1 DESIGN CONSIDERATION41
4.1.1 THE CONCEPT OF CHIP IMPLEMENTATION42
4.1.2 SIMULATION RESULTS AND MEASUREMENT ENVIRONMENT44
4.2 MEASUREMENT RESULTS47
4.2.1 THE COMPARISON OF WEIGHTED AND DISTRIBUTED METHOD WITH OUR ADAPTIVELY SEPARATED SSN METHOD48
4.2.2 HSPICE SIMULATION RESULTS OF TESTING EQUIPMENT MODEL54
4.3 SUMMARY56
CHAPTER 5
THE OVERVIEW OF USB2 SPECIFICATIONS57
5.1 INTRODUCTION57
5.2 ARCHITECTURE OVERVIEW OF USB258
5.2.1 USB2 SYSTEM DESCRIPTION58
5.2.2 USB2 PHYSICAL INTERFACE59
5.2.3 USB2 DATA FLOW TYPE60
5.2.4 USB2 BUS PROTOCOL61
5.3 OVERVIEW OF USB2 TRANSCEIVER61
5.4 SPECIFICATION OF USB2 CLOCK RECOVERY63
5.5 CONCLUSIONS64
CHAPTER 6
ALL DIGITAL CLOCK RECOVERY METHOD AND USB2 PHYSICAL LAYER DESIGN65
6.1 PROPOSED ALL DIGITAL CLOCK RECOVERY DESIGN65
6.1.1 ARCHITECTURE DESIGN OF ALL DIGITAL CLOCK RECOVERY65
6.1.2 CIRCUIT DESIGN OF ALL DIGITAL CLOCK RECOVERY 69
6.1.2.1 PHASE DETECTOR70
6.1.2.2 SHIFT REGISTER76
6.1.2.3 DELAY LINE79
6.1.3 CONCLUSIONS81
6.2 USB2 PHYSICAL LAYER DESIGN84
6.2.1 SERIAL-IN-PARALLEL-OUT (SIPO) BLOCK85
6.2.2 3-BIT COUNTER88
6.2.3 ENCODER/DECODER BLOCK89
6.2.4 SIMULATION RESULTS91
6.3 SUMMARY93
CHAPTER 7
CONCLUSIONS94

參考文獻

References
[1] W. C. Cheng, "Simultaneous Switching Noise Analysis and Synthesizer for Low Bouncing Output Driver, M.S. dissertation," Dep. Elec. Eng., National Central University, Taiwan, June. 1998.
[2] Universal Serial Bus Specification Revision 2.0, Mar. 2000.
[3] Y. T. Lin, "Investigation of Simultaneous Switching Noise for Signal Integrity in High Speed Digital Circuit Design," M.S. dissertation, Dep. Elec. Eng., National Central University, Taiwan, June. 1997.
[4] R. Senthinathan and J. L. Prince, "Application Specific CMOS Output Driver Circuit Design Techniques to Reduce Simultaneous Switching Noise," IEEE J. Solid State Circuits, vol.28, No. 12, pp.1383-1388, Dec. 1993.
[5] H. C. Chow, "CMOS Output Buffer with Reduced L-di/di Noise," United States Patent No. 5,708,386, Jan. 1998.
[6] B. A. Sharp-Geisler,, S. Jose,and Calif, "Ground Bounce Isolated Output Buffer," United States Patent No. 5,438,277, Aug. 1995.
[7] R. Senthinathan, J. L. Prince and S. Nimmagadda, "Effects of Skewing CMOS Output Driver Switching on the Simultaneous Switching Noise," 11th IEEE/CHMT International Electronics Manu. Tech. Symposium, pp. 342-345, Sept. 1991.
[8] LCB600K Cell-Based ASIC Products Design Manual, LSI Logic Corp., Nov. 1996.
[9] 0.35um Cell Library of Faraday Technology Corp.
[10] S. H. Kou, "Low Noise Output Buffer Design Techniques and Transceiver for USB2," M.S. dissertation," Dep. Elec. Eng., National Central University, Taiwan, June. 2000.
[11] A. Hatakeyama, H. Mochizuki, T. Aikawa, M. Takita, Y. Ishii, H. Tsuboi, S. Y. Fujioka, M. Koga, Y. Serizawa, K. Nishimura, K. Kawabata, Y. Okajima, M. Kawano, H. Kojima, K. Mizutani, T. Anezaki, M. Hasegawa, M. Taguchi, "A 256-Mb SDRAM Using a Register-Controlled Digital DLL," IEEE Jounal of Solid-state Circuits, Vol. 32, No. 11, November 1997.
[12] C. Y. Yang, G. K. Dehng, J. M. Hsu, S. I. Liu, "New Dynamic Flip-Flops for High-Speed Dual-Modules Prescaler", IEEE Journal of Solid-Sate Circuits, Vol. 33, No. 10, OCT. 1998.
[13] R. Goyal, "Managing Signal Integrity," IEEE Spectrum, pp. 54-58, Mar. 1994.
[14] 'Simultaneous Switching Analysis Overview," ASIC Products Application Note of IBM, Aug. 1998.
[15] S. J. Jou, W. C. Cheng and Y. T. Lin, "Simultaneous Switching Noise Analysis and Low Bouncing Buffer Design," IEEE Custom Integrated Circuits Conference, May 1998, pp.25.5.1-25.5.4.
[16] Chih-Kong Ken Yang and Mark A. Horowitz, "A 0.8-um CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links," IEEE Journal of Solid-Sate Circuits, Vol. 31, No. 12, Desember 1996.
[17] R. Vemuru, "Simultaneous Switching Noise Estimation for ASICs," IEEE International ASIC Conference and Exhibit 1995.
[18] A. Vaidyanath, B. Thoroddsen and J. L. Prince, "Effects of CMOS Driver Loading Conditions on Simultaneous Switching Noise," IEEE Trans. Comp., Packaging, Manu., Technol.-Part B, vol.17, No.4, pp.480-485, Nov.1994.
[19] R. Senthinathan and J. L. Prince, "Simultaneous Switching Ground Noise Calculation for Packaged CMOS Device," IEEE J. Solid-State Circuits, vol.26, No.11, pp.1724-1728, Nov. 1991.
[20] Sakurai and A. R. Newton, "Alpha-Power Law NOSFET Model and its Applications to CMOS Inverter Delay and other Formulas," IEEE J. Solid-State Circuits, vol.25, No.2, pp.584-594, Apr. 1990.
[21] R. Senthinathan and J. L. Prince, "Application Specific CMOS Output Driver Circuit Design Techniques to Reduce Simultaneous Switching Noise," IEEE J. Solid-State Circuits, vol.28, No.12, pp.1383-1388, Dec. 1993.

指導教授

周世傑
(Shyh-、Jye Jou)

審核日期

2000-6-16

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