適用於自動測試機台的時間產生器

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姓名

楊駿民(Chun-Min Yang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用於自動測試機台的時間產生器
(Timing Generator for the Application of the Automatic Test Equipment)

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摘要(中)

在自動測試機臺裡，時間產生器是相當重要的模組。以往這種混合式的半導體製程都是用射極耦合邏輯或砷化鎵來實現的。今日，為了降低成本和低功率的考量，CMOS製程的技術是相當吸引人的。隨著CMOS元件的性能提昇，以CMOS為基礎並能達到高解析度及微小的時間精準的時間產生器已經成為主流。
在本篇論文裡，我們提出了以延遲單元和鎖相延遲迴路為基礎的時間產生器。第一種電路是由許多延遲單元和一個校正單元組成的。它可以達到理想的單調和線性的特性並且簡化校正的程序。以鎖相延遲迴路為粗調加上一個微調電路組成了以鎖相延遲迴路為基礎的時間產生器。鎖相延遲迴路降低了因為製程和環境變異所造成的初始延遲影響。我們所提出的電路已透過臺積電和聯電的0.35μm的製程來完成。

摘要(英)

Timing generator is an important building block in Auto Test Equipment (ATE). Conventionally, it is implemented by a mixture of semiconductor technologies such as ECL or GaAs. Today, for the cost and power consumption reduction, CMOS technology is an attractive alternative. With performance improvement in CMOS devices, CMOS-based timing generators that can achieve the high resolution and small overall timing accuracy have become the main stream.
In this thesis, a delay element based timing generator and a DLL-based timing generator are proposed. The first one is composed of many delay element circuits and a calibration unit. It achieves the desired monotonicty and linearity simplifies the calibration process. The DLL-based timing generator is composed of a DLL for coarse timing generation and a fine tune circuit for the fine timing. The DLL reduces the intrinsic delay as well as the variation caused by the process and environment. The proposed circuits have been designed and implemented by TSMC 0.35μm 1P4M and UMC 0.35μm 1P3M technologies.

關鍵字(中)

★ 時間產生器
★ 延遲
★ 自動測試機臺

關鍵字(英)

★ timing generator
★ delay
★ ATE

論文目次

Contents
Chapter1Introduction 1
1.1 Motivations 1
1.2 Introduction of Timing Generator 2
1.3 Timing Generator Survey 3
1.4 Proposed Timing Generator Architecture 7
1.5 Thesis Organization 8
Chapter2Self-Calibrated Timing Generator9
2.1 Architecture Introduction 9
2.2 Specifications10
2.3 Circuit Diagram of Delay Stage11
2.4 Time-to-Digital Converter Circuit14
2.5 Test Consideration 15
2.6 Simulation Result16
2.7 Summary18
Chapter3DLL Based Timing Generator19
3.1 Architecture Introduction19
3.2 Specifications20
3.3 Delay Locked Loop21
3.4 Fine Tune Circuit27
3.5 Simulation Result28
Chapter4Chip Implementation and Testing Consideration 32
4.1 Design Flow32
4.2 Layout Implementation32
4.3 Testing Consideration37
Chapter5 Conclusion38

參考文獻

Reference
[ 1 ]Christopher W.Brason, "Integrated Pin Electronics for a VLSI Test System, " IEEE Transactions in Industrial Electronics, vol. 36, pp. 185-191, May. 1989.
[ 2 ]Jim Chapman, Jeff Currin, Steve Payne, "A Low-Cost High-Performance CMOS Timing Vernier for ATE, " IEEE International Test Conference, 1995.
[ 3 ]Jim Chapman, "High-Performance CMOS-Based VLSI Testers: Timing Control and Compensation, " IEEE International Test Conference, 1992.
[ 4 ]Tai-ichi Otsuji, Naoaki Narumi, "A 3-ns Range, 8-ps Resolution, Timing Generator LSI Utilizing Si Bipolar gate Array, " IEEE J. Solid-State Circuits, vol. 26, pp. 806-811, May. 1991.
[ 5 ] S. F. Dow, J. M. Flasck and M. E. Levi, "A CMOS Delay Locked Loop and Sub-Nanosecond Time-to-Digital Converter Chip," IEEE Transactions on Nuclear Science, vol. 43, Jun. 1996.
[ 6 ]R. E. Best, "Phase-Locked Loops Theory, Design and Applications, " Third Edition, McGraw-Hall Inc., 1996.
[ 7 ] J. Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE J. Solid-State Circuits, vol. 31, pp.1723-1732, Nov. 1996.
[ 8 ] S. Sidiropopulos and M. Horowitz, "A Semidigital Dual Delay-Locked Loop," IEEE J. Solid-State Circuits, vol. 32, pp.1683-1692, Nov. 1997.
[ 9 ] Maneatis and M. Horowitz, "Precise Delay Generation Using Coupled Oscillators," IEEE J. Solid-State Circuits, vol. 28, pp. 1273-1282, Dec. 1993.
[ 10 ] Ming-Chao Chung, "The Design and Architecture of Self-Biased Delay-Locked Loop, " Master Thesis, NCU, 1999.
[ 11 ] T. Tanabe, K. Takahashi, S. Miyamoto and M. Uesugi, "A 250~622 MHz Deskew and Jitter-Suppressed Clock Buffer Using Two-Loop Architecture," IEEE J. Solid-State Circuits, vol. 31, pp. 487-493, Apr. 1996.

指導教授

蘇朝琴(Chauchin Su)

審核日期

2000-6-14

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