博碩士論文 87324016 詳細資訊




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姓名 忻鼎昱(Ding-Yu Hsin)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 具有QAM/VSB 模式之多重組態可適應性等化器的設計與實現
(Design and Implementation of Multi-states Adaptive Equalizer with QAM/VSB Mode)
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摘要(中) 在本篇論文中,我們提出了一個可適用於正交振幅調變(Quadrature Amplitude Modulation)以及殘邊帶調變(Vestigial SideBand Modulation)的可適應性等化器。此等化器主要是由分數間距等化器(Fractionally Spaced Equalizer),決策回授等化器(Decision Feedback Equalizer)以及決策元件所組成。其中分數間距等化器及決策回授等化器皆是使用數位有限脈衝響應濾波器(Digital Finite Impulse Response Filter)配合有號延遲最小均方根值演算法(Sign-Delayed LMS algorithm)。同時為了增強等化器的效能,我們使用了多重階段演算法(Multi-stage algorithm),停和走演算法(Stop-and-Go algorithm)以及降低誤差增值演算法(Reduction of Error Propagation algorithm)。在殘邊帶調變模式中,引導頻帶(pilot tone)將會降低等化器的效能,所以我們使用了一個引導頻帶消除器(pilot tone canceller)在此等化器中。在硬體實現方面,由於需要複數數系的運算,因此每個等化器皆需用四個濾波器,而每個濾波器皆由重複使用乘和累加運算來實現。同時反旋轉器(Derotator)也使用了同樣的方式來降低硬體複雜度。為了達到低功率消耗的目的,我們使用隨機存取記憶體(RAM)來取代傳統的移位暫存器(Shift Register)。此等化器的資料傳送速率為5.38MHz,內部工作頻率為64.56MHz。我們使用 Avanti 0.35um元件庫(Cell library)來實現晶片。整個晶片的閘數(Gate Count)大約為六萬多個。
摘要(英) A dual mode adaptive equalizer suitable for Quadrature Amplitude Modulation (QAM) system and Vestigial SideBand (VSB) modulation system is present. The adaptive equalizer consists of Fractionally Spaced Equalizer (FSE), Decision Feedback Equalizer (DFE), and decision device. Both of the FSE and DFE are the 18 taps linear transversal filters with Sign-Delayed LMS algorithm. To improve the equalizer performance, the multi-stage algorithm, the stop-and-go algorithm, and the reduction of error propagation algorithm is present. In VSB mode, the pilot tone will degrade the performance of equalizer so that a pilot tone canceller is necessary in our equalizer. In the previous design, the equalizer can’t perform well in all channel models. Due to the performance enhancement in this design, it can converge in all channel models. Both the FSE and DFE have four filters due to the complex number operations. We implement each filter by reusing MAC operations. Also the derotator uses the same methodology to reduce the hardware complexity. The RAM structure is used to replace the shift register for low power consideration. The symbol rate is 5.38 MHz and the internal operation frequency is 64.56MHz. We use the Avanti Cell Library and TSMC 0.35um CMOS 1P4M technology for chip implementation. The gate count of chip is about 63000.
關鍵字(中) ★ 等化器
★ 可適應性濾波器
★ 有線電視
關鍵字(英) ★ equalizer
★ adaptive filter
★ CATV
論文目次 Contents
1 Introduction………………………………………1
1.1Motivation……………………………………………………1
1.2Dual Mode System……………………………………………4
1.3Thesis Organization……………………………………………5
2 Overview of the CATV Transceiver…………………6
2.1 Transmitter……………………………………………………6
2.2 Receiver…………………………………………………………8
2.2.1 VSB Mode Operation…………………………………9
2.2.2 QAM Mode Operation………………………………11
2.3 Summary…………………………………………………12
3 Dual Mode Adaptive Equalizer………………………13
3.1 Introduction of Equalizer…………………………………13
3.1.1 Linear Transversal Equalizer………………………13
3.1.2 Fractionally Spaced Equalizer……………………15
3.1.3 Decision Feedback Equalizer………………………17
3.2 Adaptive Algorithm………………………………………19
3.2.1 LMS Algorithm…………………………………20
3.2.2 Sign-LMS Algorithm……………………………20
3.2.2 Sign-Delayed LMS Algorithm………………………21
3.3 Improvement of LMS Algorithm…………………………22
3.3.1 Stop & Go Algorithm…………………………………22
3.3.2 Multistage Algorithm…………………………………23
3.4 Reduction of Error Propagation in DFE……………………23
3.5 System Simulation Results…………………………………25
4 Architecture of Proposed Equalizer……………………29
4.1 Introduction………………………………………………29
4.2 The Architecture Design of Proposed Equalizer…………29
4.2.1 Design Specificaton………………………………30
4.2.2 Fractionally Spaced Equalizer……………………31
4.2.3 Decision Feedback Equalizer………………………34
4.2.4 Multi-Stage Slicer……………………………………35
4.2.5 Coefficients Update Block and Pilot Tone Canceller…36
4.3 The RTL Level Design of Proposed Equalizer………………38
4.3.1 Design Specification………………………………38
4.3.2 Fractionally Spaced Equalizer……………………39
4.3.3 Decision Feedback Equalizer………………………43
4.3.4 Multi-Stage Slice……………………………………45
4.3.5 Coefficients Update Block and Pilot Tone Canceller…47
4.4 Low Power Consideration………………………………50
4.5 Summary of Dual Mode Equalizer……………………………52
5 Chip Implementation…………………………………53
5.1 Introduction and Design Flow………………………………53
5.2 Testing Consideration...……………………………………55
5.3 Chip Summary…………………………………………56
6 Conclusion……………………………………………58
References………………………………………………59
參考文獻 References
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[2]S. C. Hsieh, H. H. Tseng, “A QAM Equalizer Chip Design Implementation and Testing,” TL Tech. J., vol. 25-5, pp.893-903, Oct. 1995.
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[10]F. Lu, H. Samueli, “A 60-MBd, 480-Mb/s, 256-QAM Decision-Feedback Equalizer in 1.2-mm CMOS,” in IEEE J. Solid State Circuits, vol. 28, no. 3, pp. 330-338, Mar. 1993.
[10]F. Lu, H. Samueli, “A 60-MBd, 480-Mb/s, 256-QAM Decision-Feedback Equalizer in 1.2-mm CMOS,” in IEEE J. Solid State Circuits, vol. 28, no. 3, pp. 330-338, Mar. 1993.
[10]F. Lu, H. Samueli, “A 60-MBd, 480-Mb/s, 256-QAM Decision-Feedback Equalizer in 1.2-mm CMOS,” in IEEE J. Solid State Circuits, vol. 28, no. 3, pp. 330-338, Mar. 1993.
[13]Rong-Yu Yen, ”Implementation of Carrier Recovery and Timing Recovery for QAM/VSB mode CATV system,” Master Thesis, National Centeral University, 1999
[14]S. Haykin, Adaptive Filter Theory, 3rd. ed., Prentic Hall, 1996.
[15]Bernard. Sklar, Digital Communications Fundamentals and Applications, Prentice Hall, 1996.
[16]M. T. Shiue, ”Transceiver VLSI Design High Speed Local Access Modems,” Ph.D Theris, National Centeral University, 1998.
[17]A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-Power CMOS Digital Design,” IEEE JSSC, vol. 27, pp473-484, Apr. 1992.
[18]Chih-Feng Wu, “QAM/VSB Dual Mode Equalizer Design and Implementation,” Master Thesis, National Centeral University, 1998
指導教授 周世傑(Shyh-Jye Jou) 審核日期 2000-7-18
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