以改良式向量旋轉器為核心的遞迴式傅立葉模組設計

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：131

、訪客IP：3.142.174.55

姓名

俞已立(Chi-Li Yu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

以改良式向量旋轉器為核心的遞迴式傅立葉模組設計
(A Cost-Effective Time-Recursive FFT architecture Based on Improvement Vector Rotator for DMT Transmitter)

相關論文

★ 適用於通訊系統之李德所羅門軟性智慧財產模組自動產生器	★ 適用於RSA公匙密碼系統之高效能Montgomery模組
★ 適用於非對稱數位用戶迴路系統之有效率的時域等化器演算法	★ 第二代高速數位用戶迴路中維特比解碼器之FPGA實現
★ 一個高速╱低複雜度旋轉方法的統一設計架構：角度量化的觀點

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

離散多頻調變技術(DMT)是非對稱數位用戶迴路(ADSL)的實體層傳輸標準，它能克服傳統電話雙絞線的傳輸瓶頸，達到高速傳輸速率的要求。但是，高度的運算/硬體複雜度是DMT的主要缺點，而構成調變核心的傅立葉/反傅立葉轉換(FFT/IFFT)模組則特別地複雜。在這篇論文中，我們採用時間遞迴式傅立葉轉換架構來實現DMT發射器裡的反傅立葉轉換模組。為了減少該模組的遞迴次數，我們重新排列組合輸入信號，使得遞迴次數減半，而硬體複雜度也因此得到化減。
此外，由於該時間遞迴式傅立葉轉換架構的核心是一個以乘法器為基礎的旋轉器，為使硬體複雜度進一步減少，我們以數位座標旋轉計算器(CORDIC)來取代它。在回顧一些以CORDIC為基礎的旋轉器後，我們選擇使用擴大的基本角度集合CORDIC (EEAS-CORDIC)，因為它具有運算快速的優點。接著我們發展出一套設計流程來減低EEAS-CORDIC裡位移器的面積，根據模擬結果，在透過這套設計流程後，位移的閘數可減少51%，而新型CORDIC的總體雜數則可減低32%。並且，當新CORDIC與修改過的時間遞迴式反傅立葉轉換模組結合後，速度及精確度也都能符合規格的要求。總體來說，上述的改進使得新的反傅立葉轉換模組更適合於超大型積體電路實現。

摘要(英)

Discrete Multitone modulation (DMT) is the physical-layer transmission standard of Asymmetric Digital Subscriber Line (ADSL). It can achieve rate-adaptive high-speed transmission over twisted-pair copper lines in telephone carrier serving areas (CSA). But, one major disadvantage of the DMT scheme is its high computational/hardware complexity, especially for the IFFT/FFT operations that form the multitone processing kernels. In this thesis, we employ time-recursive FFT architecture to realize the IFFT module in DMT transmitter. To reduce the iteration number of the time-recursive IFFT, we reorder the input data. Hence, the iteration number is halved and the hardware complexity is reduced, too.
Furthermore, we employ Cordinate Rotation Digital Computer (CORDIC) to replace the multiplier-based rotator, which is the original kernel of the time-recursive IFFT. After reviewing some CORDIC-based rotators, we choose Extended Elementary-Angle Set CORDIC (EEAS-CORDIC) due to its high performance of speed. A new design flow is also developed to reduce the hardware complexity of the shifters in EEAS-CORDIC. By going through this flow, the gate count of all shifters is reduced 51%, and overall gate count of new CORDIC is saved 32%. Simultaneously, the speed and accuracy performance can also achieve the specification after combining the modified time-recursive IFFT and the new CORDIC. By the improvements of our work, the new IFFT module is more suitable for practical implementation.

關鍵字(中)

★ 快速傅立葉轉換
★ 座標旋轉數位計算器
★ 非對稱數位用戶迴路
★ 離散多頻調變技術

關鍵字(英)

★ FFT
★ CORDIC
★ ADSL
★ DMT

論文目次

Chapter 1 : INTRODUCTION
Chapter 2 : TIME-RECURSIVE IFFT IN DMT TRANSMITTER
Chapter 3 : REVIEW OF CORDIC-BASED ROTATORS
Chapter 4 : PROPOSED REEAS-CORDIC
Chapter 5 :ARCHITECTURE MAPPING AND SIMULATION RESULT
Chapter 6 : CONCLUSION

參考文獻

[1] G. H. Im, D. D. Harman, G. Huang, A. V. Mandzik, M. H. Nguyen, and J. J. Werner, ?.84 Mb/s 16-CAP ATM LAN standard," IEEE J. Select. Areas Commum., vol. 13, pp. 620-632, May 1995.
[2] J. S. Chow, J. C. Tu, and J. M. Cioffi, "A discrete multitone transceiver system for HDSL applications," IEEE J. Select. Areas Commun., vol. 9, pp. 895-908, Aug. 1991.
[3] K. Sistanizadeh, P. Chow, and J.M. Cioffi, "Multi-tone transmission for asymmetric digital subscriber lines (ADSL)," in Proc. ICC'93, pp. II. 756-760.
[4] I. Lee, J. S. Chou, and J. M. Cioffi, "Performance evaluation of a fast computation algorithm for the DMT in high-speed subscriber loop, " IEEE J. Select. Areas Commun., vol. 13, pp. 1560-1570, Dec. 1995.
[5] T. N. Zogakis, J. T. Aslanis Jr., and J. M. Cioffi, "A coded and shaped descrete multitone system," IEEE Trans. Commun., vol. 43, pp. 2941-2949, Dec. 1995.
[6] B. Daneshrad and H. Smueli, "A 1.6 Mps digital-QAM system for DSL transmission," IEEE J. Select. Areas Commun., vol. 13, pp. 1600-1610, Dec. 1995.
[7] Network and customer installation interface-Asymmetric digital subscriber line (ADSL) metallic interface. ANSI TI.413, 1995.
[8] J. L. Holsinger, "Digital communication over fixed time continuous channels with memory," Pj.D. dissertations, M.I.T. 1964.
[9] R. W. Chang, "High-speed multichannel data transmission with bandlimited orthogonal signals," Bell Syst. Tech. J., vol. 45, pp. 1775-1796, Dec. 1966.
[10] B. R. Saltzberg, "Performance of an efficient parallel data transmission system," IEEE Trans. Commun. Technol., vol. COM-15, pp. 805-811, Dec. 1967.
[11] S. B. Weinstein and P. M. Ebert, "Data transmission by frequency-division multiplexing using the discrete Fourier transform," IEEE Trans. Commun., vol. COM-19, pp. 628-634, Oct. 1971.
[12] A. Peled and A. Ruiz, "Frequecy domain data transmission using reduced computational complexity algorithms," IEEE Int. Conf. Acoust., Speech, and Signal Processing, Denver, CO, pp. 964-967, Apr. 1980.
[13] J. A. C. Bingham, "Multicarrier modulation for data transmission: An idea whose time has come," IEEE Commun. Mag., vol. 28, no. 5, pp. 5-14, May 1990.
[14] P. S. Chow, J. C. Tu, and J. M. Cioffi, "Performance for a multichannel transceiver system for ADSL and VHDSL services," IEEE J. Select. Areas Commun., vol. 9, no. 6, pp. 909-919, Aug. 1991.
[15] K. S. Jacobsen and J. M. Cioffi, "An efficient digital modulation scheme for multimedia transmission on the cable television network," In Technical Papers, 43rd Annual National Cable Television Association (NCTA) Convention and Exposition, New Orleans, LA, May 1994.
[16] J. S. Chow, J. M. Cioffi, and A. C. Bingham, "Equalizer training algorihtms for multicarrier modulation systems," IEEE Int. Conf. Commun., 1993.
[17] D. D. Falconer and Jr. F. R. Magee, "Adaptive channel memory truncation for maximum likelihood sequence estimation," Bell Syst. Tech. J., 52:1541-1562, Nov. 1973.
[18] D. G. Messerschmitt, "Design of a finite impluse response for the Viterbi algorithm and decision feedback equalizer," Int. Conf. Commun., pp. 73D.1-5, June 1974.
[19] J. A. C. Bingham, "The theorem and practice of modem design," John Wiley & Sons, New York, NY, 1988.
[20] G. Ungerboeck, "Channel coding with multilevel/phase signals," IEEE Trans. Information Theory, vol. 28, pp. 55-67, Jan. 1982.
[21] G. D. Forney, Jr., "Efficient odulation for band-limited channels," IEEE J. Select. Areas Commun., vol. 2, pp. 632-647, Sept. 1984.
[22] L. -F. Wei, "Trellis-coded modulation with multidimensional constellations," IEEE Trans. Information Theory, vol. 33, pp. 483-501, July 1987.
[23] J. E. Volder, "The CORDIC trigonometric technique," IRE Trans. On Electronic Computers, vol. 8, pp. 330-334, Sept. 1959.
[24] J. S. Walther, "A unified algorithm for elementary functions," Spring Joint Computer Conf., pp. 379-385, 1971.
[25] Y. H. Hu and S. Naganathan, "An angle recoding method for CORDIC algorithm implementation," IEEE Trans. On Computers, vol. 42, pp. 99-102, Jan. 1993
[26] A. V. Oppenheim and R. W. Schafer, Discrete-time Signal Processing. Prentice Hall, 1989.
[27] A. Y. Wu and T. S. Chan, "Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology," IEEE Int. Conf. Acoust., Speech, and Signal Processing, vol. 6, pp. 3517-3520, Apr. 1998.
[28] C. S. Wu and A. Y. Wu, "A New CORDIC Algorithm and Architecture Based on Extended Elementary-angle Set and Trellis-based Searching Schemes," is submitted to IEEE Trans. Signal Processing.
[29] K. J. Ray Liu, C. T. Chiu, R. K. Kolagotla, and J. F. J'aJ'a, "Optimal unified architectures for the real-time computation of time-recursive discrete sinusoidal transforms," IEEE Trans. Circuits and Systems for Video Technology, vol. 4, no. 2, pp. 168-180, Apr. 1994.
[30] K. J. Ray Liu, and C. T. Chiu, "Unified parallel lattice structures for time-recursive discrete cosine/sine/Hartley transforms," IEEE Trans. Signal Processing, vol. 41, no. 3, pp. 1357-1377, Mar. 1993.
[31] Y. H. Hu, "CORDIC-based VLSI architectures for digital signal processing," IEEE Signal Processing Magazine, pp. 16-35, July 1992.
[32] C. T. Chan, "Cost-efficient VLSI Implementation of the IFFT/FFT Processing Kernel in DMT Transceiver," Master Thesis, Dep. Of Electrical Engineering, NCU, 1998.
[33] S. J. Yih, M. Cheng, and W. S. Feng, "Multilevel barrel shifter for CORDIC design," Electronics Letters, vol. 32 13, pp. 1178-1179, June 1996.
[34] P. P. Vaidyanathan, "A unified approach to orthogonal digita filters and wave digital filters based on the LBR two-pair extraction," IEEE Trans. Circuits Syst., pp. 673-686, July 1985.
[35] A. Y. Wu, K. J. R. Liu, and A. Raghupathy, "System architecture of an adaptive reconfigurable DSP computing engine," IEEE Trans. Circuits Syst. Video Technol., vol. 8, pp. 54-73, Feb. 1998.
[36] E. F. Deperttere, P. Dewilde, and R Udo, "Pipelined CORDIC architectures for fast VLSI filtering," in Proc. IEEE Int. Conf. On ASSP, pp. 1-4, 1984.
[37] A. M. Despain, "Very fast Fourier transform algorithms for hardware implementation," IEEE Trans. On Computers, vol. 28, pp. 333-341, May 1979.
[38] L. W. Chang and S. W, Lee, "Systolic arrays for the discrete Hartley transform," IEEE Trans. On Signal Processing, vol. 29, pp. 2411-2418, Nov. 1991.

指導教授

吳安宇(An-Yeu Wu)

審核日期

2000-7-13

推文