姓名 郭晉瑋(Chin-Wei Kuo) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 次微米金氧半場效應電晶體大訊號模型及其在高速通訊電路之應用
(The large-signal model of complementary MOSFETs and its applications in high speed communication circuits)
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摘要(中) 摘 要
根據在第二章節中建立起的高頻大訊號模型，我們分別設計了操作在2.4 GHz頻段的壓控振盪器、低雜訊放大器、降頻用的雙平衡混波器以及降頻電路。在壓控震盪器方面，此震盪器的振盪頻率與輸出功率可以從2.34 GHz的-5 dBm到 2.45 GHz的4 dBm，其可調振盪頻率可以達到183 MHz/V. 而在雜訊方面，此振盪器在2.4 GHz的振盪頻率下其相位雜訊在100 KHz與1 MHz的偏移下分別可以達到-89 dBc/Hz與 –110 dBc/Hz。在低雜訊放大器方面，是採用共源極組態利用電感式衰減模式的架構以達到較高的功率增益以及較低的雜訊指數；此低雜訊放大器在2.4 GHz的操作頻段下，擁有14 dB的功率增益以及2.1 dB的最低雜訊指數；在其線性度的考量方面，此放大器的功率1dB壓縮點(P1dB)及輸入三次斜波截止點 (IIP3)分別發生在輸入功率為-4dBm與0 dBm的時候。此外，在降頻專用吉爾伯雙平衡式混波器的設計方面， 此混波器提供了3 dB的功率增益，它的的功率1dB壓縮點(P1dB)發生在輸入功率為-5 dBm的時候；在隔絕度方面，此混波器射頻輸入端到中頻輸出端的隔絕度在不同的射頻輸入功率下都有超過18 dB的表現，而本地訊號輸入端到中頻輸出端的隔絕度都超過33 dB。在此混波器的線性度方面，其輸入三次斜波截止點 (IIP3)發生在輸入功率為0 dBm的時候。在此章節的最後我們設計了一個2.4 GHz的降頻器，此降頻器可以將輸入為2.45 GHz的射頻訊號轉換成80 MHz的中頻訊號並提供了12 dB的轉換增益；此降頻器消耗了 80 mW的直流功率且其功率1dB壓縮點(P1dB)及輸入三次斜波截止點 (IIP3)分別發生在輸入功率為-12dBm與12 dBm的時候。
最後再第五章裏，我們設計了應用在光纖通訊系統中的轉阻放大器以及一級的限制放大器。我們利用電容式與電感式不同型式的突起來設計轉阻放大器。在電容式突起的轉阻放大器中，再不犧牲到低頻增益的條件下，我們利用一並聯式電容突起的方式使此轉阻放大器的3 dB頻寬從原來的875 MHz增加到1.35 GHz。在電感式突起的設計中，我們利用了閘極端點感式突起與汲極端感式突起兩種方式來設計此轉阻放大器；不論是哪一種電感式突起的設計都可以在不犧牲低頻增益下改善原有的操作頻寬。然後汲極端電感式突起的設計在眼圖方面的考量下，可以的到清晰不失真的眼圖。在限制放大器方面，我們設計了一個應用在傳輸速度為7Gbps的一級差動限制放大器，此限制放大器擁有13.8 dB的功率增益與4.4 GHz的3dB頻寬。
摘要(英) In near decades, the rapid growth of optical and wireless communication systems market drive optical and radio frequency integrated circuits into a higher level integration with lower power consumption. To achieve these goals, the designers have to integrate the discrete circuits on the same substrate to reduce the size and the cost. However, with the scaling down of the CMOS channel length into deep sub-micrometer scale, the characteristic of CMOS device could be improved for GHz application.
In the chapter 2, this thesis survey the modified MOSFET RF large-signal model in 0.18 mm CMOS technologies for optical and the RF circuits design. The modified large-signal model consists of a conventional BSM3v3 model and the passive networks which represent the parasistic effects of the MOSFET.
In the chapter 3, this study proposed a self-define large-signal model for 50 mm-wide nMOS transistor. The self-defined model can predict not only dc and microwave performance well but also in noise characteristics by using P, R, C noise parameters calculation. In this empirical model, all the parameters were extracted from measurement results; moreover, the intrinsic parameters could be characterized as functions of the gate to source voltage (Vgsi) and drain to source voltage (Vdsi).
Moreover, in the chapter 4, various RF circuits are presented based on the modified RF large-signal model described in the chapter 2. The RF circuits include a 2.4 GHz voltage-controlled oscillator, a 2.4 GHz low-noise amplifier, a double-balanced mixer and a 2.4 GHz down-converter. Most of the circuits use the MOSFET RF large-signal model described in the chapter 2. The voltage-controlled oscillator delivered –5 dBm to 4 dBm as the oscillated frequency moved from 2.34 GHz to 2.45 GHz, which resulted in a tuning factor of 183 MHz/V. Furthermore, the phase noise of the VCO is –110 dBc/Hz with a 1MHz offset at 2.4 GHz operation. Besides, the 2.4 GHz low-noise amplifier with common-source inductive degeneration architecture was presented. The LNA has the power gain of 14 dB at 2.4 GHz with a Fmin of 2.1 dB; as to the linearity behaviors, the P1dB and and the IIP3 of the LNA are –4 dBm and 0 dBm, respectively. Moreover, the double-balance Gilbert cell mixer was introduce for the down-conversion application, the mixer provide the conversion of 3 dB with a P1dB of –5 dBm; the RF-to-IF isolations are all greater than 18 dB and the LO-to-IF isolation can achieve 33 dB. As to the consideration of linearity, the IP3 of the mixer is located at input power of 0 dBm. At the last, a 2.4 GHz down-converter was proposed, which converts the 2.45 GHz RF signal to 80 MHz IF signal with the conversion of 12 dB and consuming 80 mW of DC power. Also, the P1dB and IIP3 of the CMOS down-converter is –12 dBm and –2 dBm.
In the chapter 5, the optical transimpedance amplifiers and one stage limiting amplifier were presented. Here we used two peaking mechanisms for the TIA design namely, capacitive peaking and inductive peaking. In the TIAs design with the capacitive peaking approach, the 3 dB bandwidth can be enhanced from 875 MHz to 1.35 GHz without sacrificing its low-frequency gain. As to the inductive peaking design, both gate-inductive peaking and drain inductive peaking were presented in this chapter. By using the gate and drain inductive peaking approach, the 3-dB bandwidth could be improved from 4.4 GHz to 6.8 GHz and from 4.4 GHz to 6.8 GHz, however, the drain-inductive peaking demonstrated the superior characteristics in the output eye patterns. On the part of limiting amplifier, a one stage LA for 7 Gbps application was fabricated and characterized with the fully differential topology, which has the power gain of 13.8 dB and the 3 dB bandwidth can up to 4.4 GHz.
關鍵字(中) ★ 大訊號模型
關鍵字(英) ★ power contour
★ large-signal model
論文目次 TABLE OF CONTENTS
Figure captions VIII
Table captions XIII
Chapter 1 Introductions
1-1. Motivation 1
1-2. Thesis Organization 2
Chapter 2 The Modified MOSFET Scaleable RF Large-Signal Model
2-1. Introduction 4
2-2. MOSFET Device Layout 5
2-3. Scaleable RF Large-Signal Model for 0.18-mm MOSFETs 8
2-4. Passive Component Models 22
2-4-1. The equivalent circuit model of spiral inductors 22
2-4-2. The equivalent circuit model of MIM capacitors 26
2-5. Summary 28
Chapter 3 The Self-Defined Empirical MOSFER RF Large-Signal Model
3-1. Introduction 29
3-2. MOSFET Large-Signal Model and Parameter Extraction 30
3-2-1 The extractions of the DC-related parameters and I-V prediction 31
3-2-2 The extractions of the extrinsic components 33
3-2-3 The microwave and power performance prediction 35
3-3. The prediction of noise performance 39
3-3-1 Parameters of the thermal noise 39
3-3-2 High frequency noise model of nMOSFET 41
3-4. The design of Low noise amplifier with different models 42
3-5. Summary 46
Chapter 4 CMOS RF Circuits Design
4-2. The Microwave Voltage-Controlled Oscillators 49
4-2-1 Basic concept of the cross-coupled oscillator 49
4-2-2 The 2.4 GHz Monolithic CMOS voltage-controlled oscillator 52
4-3. The Microwave Low-Noise Amplifier 56
4-3-1 Basic concept of the LNA 56
4-3-2 Topologies of the LNA 57
4-3-3 The 2.4 GHz low-noise amplifier design 61
4-4. The Microwave Gilbert-Cell Mixer 62
4-4-1 Basic concept of the Gilbert-cell mixer 66
4-4-2 The Monolithic CMOS double-balanced Gilbert-cell Mixer 67
4-5. The Microwave Down-Converter 72
4-5-1 The architecture of the 2.4 GHz CMOS down-converter 72
4-5-2 The architecture of the 2.4 GHz CMOS down-converter 72
4-6. Summary 77
Chapter 5 CMOS Integrated Circuits for Optical Communications
5-1. Introduction 78
5-2. The Design of Transimpedance Amplifier 79
5-2-1 The TIA design with the capacitive peaking mechanism 80
5-2-2 The TIA design with the inductive peaking mechanism 86
5-3. The Design of limiting Amplifier 102
5-3-1 The technique of broadband design in limiting amplifier 102
5-3-2 The design of the limiting amplifier 104
5-3-3 The experimental results 105
5-4. Summary 108
Chapter 6 Conclusions 109
Publication List 118
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指導教授 詹益仁(Yi-Jen Chan) 審核日期 2003-9-29 推文 facebook plurk twitter funp google live udn HD myshare reddit netvibes friend youpush delicious baidu