參考文獻 |
[1] Y. Leblebici, M.S. Unu, H. Morkoc and S.M. Kang, “One-dimensional Transient
Device Simulation Using a Direct Method Circuit Simulator.” Department of Electrical and Computer Engineering and Coordinated Science Laboratory.
[2] F. Yamamoto and S. Takahashi, “Vectorized LU decomposition algorithms for
large-scale circuit simulation.” IEEE Trans. Computer-Aided Design, vol. CAD-4, no.3, pp. 232-238, July 1985.
[3] H. C. Elman, “Iteration methods for large, sparse, nonsymmetric systems of linear
equations.” Ph.D. dissertation, Res. Rep. 229, Dep. Comput. Sci., Yale Univ., 1982.
[4] R. A. Saleh, J. E. Kleckner, and A. R. Newton, “Iterated timing analysis and SPLICE1,” in Proc. ICCAD-83, pp. 139-140, Sept. 1983.
[5] P. Sonneveld, “CGS, A fast Lanezos-type Solver for nonsymmetric linear systems,” SIAM J. Sci. Stat. Comput., vol. 10, no. 1, pp. 36-52, 1989.
[6] Karl-Michael Eickhoof, and Walter L. Engl, “Levelized Incomplete LU Factorization and Its Appplication to Large-scale Circuit Simulation”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no.6, pp. 720-727, June 1995.
[7] Zhong-Yi Zhao, Qi-Ming Zhang, Gen-Lin Tan, and J. M. Xu, “A New Preconditioner for CGS Iteration in Solving Large Sparse Nonsymmetric Linear Equations in Semiconductor Device Simulation.” IEEE Transactions on Computer-Aided Design, vol. 10, no. 11, November 1991.
[8] Jiri Vlach, Kishore Singhal, “Computer methods for circuit analysis and design.”, pp. 428-430, Van Nostrand Reinhold, New York, 1994.
[9] C. Y. Lee, “Levelized Incomplete LU factorization and Its application to semiconductor devices.” M. S. thesis, National Central University, Taiwan, Republic of China, June 1998.
[10] P. C. H. Chan and C. T. Sah, “Exact Equivalent Circuit Model for Steady-state Characterization of Semiconductor Devices with Multiple-Energy-Level Recombination Centers.” IEEE Transactions Electron Devices, vol. ED-26, no. 6, pp. 924-936, 1979.
[11] Kartikeya Mayaram, Member, IEEE and Donal O. Pederson, Fellow, “Coupling Algorithms for Mixed-Level Circuit and device Simulation.”, IEEE Transactions on Computer-Aided Design, vol. 11, no.8, August 1992.
[12] Y. T. Yeow, C. H. Ling, “Teaching Semiconductor Device Physics with Two-Dimensional Numerical Solver.”, IEEE Transactions on Education. vol. 42, no.1, Feb. 1999.
[13] H. CRAIG CASEY, JR, “Device for Integrated Circuits, Silicon and III-V Compound Semiconductors.” Chapter 8, JOHN WILEY & SONS, INC.
[14] R. S. Varga, “Matrix Iterative Analysis,” Englewood Cliffs, NJ: Prentice-Hall, 1962. |