博碩士論文 87324034 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:10 、訪客IP:3.140.185.147
姓名 蔡木凱(Mu-Kai Tai)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 改善後的階層化不完全LU法及其在二維半導體元件模擬上的應用
(An Improved Levelized Incomplete LU Method and Its Application to 2D Semiconductor Device Simulation)
相關論文
★ 表面電漿共振效應於光奈米元件之數值研究★ 金氧半電容元件的暫態模擬之數值量測
★ 雙載子電晶體在一維和二維空間上模擬的比較★ 一維雙載子接面電晶體數值模擬之驗證及其在元件與電路混階模擬之應用
★ 階層化不完全LU法及其在準靜態金氧半場效電晶體電容模擬上的應用★ 探討分離式簡化電路模型在半導體元件模擬上的效益
★ 撞擊游離的等效電路模型與其在半導體元件模擬上之應用★ 二維半導體元件模擬的電流和電場分析
★ 三維半導體元件模擬器之開發及SOI MOSFET特性分析★ 元件分割法及其在二維互補式金氧半導體元件之模擬
★ 含改良型L-ILU解法器及PDM電路表述之二維及三維元件數值模擬器之開發★ 含費米積分之高效率載子解析模型及其在元件模擬上的應用
★ 量子力學等效電路模型之建立及其對元件模擬之探討★ 適用於二維及三維半導體元件模擬的可調變式元件切割法
★ 整合式的混階模擬器之開發及其在振盪電路上的應用★ 用時域模擬法探討S參數及其應用
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 在積體電路的設計和發展上,半導體的數值模擬分析扮演一個非常重要的角色。一些在實驗上或解析模型上觀察不到的元件電性,就可藉由元件的模擬來觀察。但是在半導體元件的數值模擬過程中,往往需要解非常龐大的稀疏矩陣,所以在本論文中,將就半導體元件的模擬特性來改善階層化不完全LU分解法 (Levelized Incomplete LU method),並用來開發一個新的稀疏矩陣解法器。而在元件和半導體的混階模擬上,我們將描述載子傳輸的擴散模型藉由專業的技術加以分離,以轉換成一些等效電路元件,例如電壓控電流源、電容和電壓控制電壓源等。因此就可使用一般的電路模擬器來做混階模擬。 最後,我們將使用二極體開關電路和金氧半場效電晶體,配合新的電路模擬器進行一維和二維混階模擬,並對元件的特性進行分析和討論。在模擬過程中,我們也會比較改善後的矩陣解法和傳統解法在模擬速度上的差異。
關鍵字(中) ★ 階層化
★ 不完全LU
★ 混階
★ 模擬
關鍵字(英) ★ levelized
★ incomplete lu (ILU)
★ mixed-level
★ simulation
論文目次 1. Introduction
2. Levelized Incomplete LU Method
2.1 Levelized Incomplete LU Method
2.2 Programming Techniques for Levelized Incomplete LU Method
2.2.1 Symbolic Factorization
2.2.2 Numerical Factorization
2.3 The Iteration Scheme
3. One-dimensional Semiconductor Device Simulation
3.1 1D Equivalent Circuit Model Development
3.2 Simulation of PN Diode Switching Circuit
3.3 An Improved Levelized Incomplete LU Method
4. Two-dimensional Semiconductor Device Simulation
4.1 2D Equivalent Circuit Model Development
4.2 2D Simulation of PN Diode Switching Circuit
4.3 Simulation of MOSFET Characteristics
4.3.1 Simulation of MOSFET DC i-v Characteristics
4.3.2 Simulation of MOSFET Subthreshold Current Behavior
5. Conclusion
參考文獻 [1] Y. Leblebici, M.S. Unu, H. Morkoc and S.M. Kang, “One-dimensional Transient
Device Simulation Using a Direct Method Circuit Simulator.” Department of Electrical and Computer Engineering and Coordinated Science Laboratory.
[2] F. Yamamoto and S. Takahashi, “Vectorized LU decomposition algorithms for
large-scale circuit simulation.” IEEE Trans. Computer-Aided Design, vol. CAD-4, no.3, pp. 232-238, July 1985.
[3] H. C. Elman, “Iteration methods for large, sparse, nonsymmetric systems of linear
equations.” Ph.D. dissertation, Res. Rep. 229, Dep. Comput. Sci., Yale Univ., 1982.
[4] R. A. Saleh, J. E. Kleckner, and A. R. Newton, “Iterated timing analysis and SPLICE1,” in Proc. ICCAD-83, pp. 139-140, Sept. 1983.
[5] P. Sonneveld, “CGS, A fast Lanezos-type Solver for nonsymmetric linear systems,” SIAM J. Sci. Stat. Comput., vol. 10, no. 1, pp. 36-52, 1989.
[6] Karl-Michael Eickhoof, and Walter L. Engl, “Levelized Incomplete LU Factorization and Its Appplication to Large-scale Circuit Simulation”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no.6, pp. 720-727, June 1995.
[7] Zhong-Yi Zhao, Qi-Ming Zhang, Gen-Lin Tan, and J. M. Xu, “A New Preconditioner for CGS Iteration in Solving Large Sparse Nonsymmetric Linear Equations in Semiconductor Device Simulation.” IEEE Transactions on Computer-Aided Design, vol. 10, no. 11, November 1991.
[8] Jiri Vlach, Kishore Singhal, “Computer methods for circuit analysis and design.”, pp. 428-430, Van Nostrand Reinhold, New York, 1994.
[9] C. Y. Lee, “Levelized Incomplete LU factorization and Its application to semiconductor devices.” M. S. thesis, National Central University, Taiwan, Republic of China, June 1998.
[10] P. C. H. Chan and C. T. Sah, “Exact Equivalent Circuit Model for Steady-state Characterization of Semiconductor Devices with Multiple-Energy-Level Recombination Centers.” IEEE Transactions Electron Devices, vol. ED-26, no. 6, pp. 924-936, 1979.
[11] Kartikeya Mayaram, Member, IEEE and Donal O. Pederson, Fellow, “Coupling Algorithms for Mixed-Level Circuit and device Simulation.”, IEEE Transactions on Computer-Aided Design, vol. 11, no.8, August 1992.
[12] Y. T. Yeow, C. H. Ling, “Teaching Semiconductor Device Physics with Two-Dimensional Numerical Solver.”, IEEE Transactions on Education. vol. 42, no.1, Feb. 1999.
[13] H. CRAIG CASEY, JR, “Device for Integrated Circuits, Silicon and III-V Compound Semiconductors.” Chapter 8, JOHN WILEY & SONS, INC.
[14] R. S. Varga, “Matrix Iterative Analysis,” Englewood Cliffs, NJ: Prentice-Hall, 1962.
指導教授 蔡曜聰(Yao-Tsung Tsai) 審核日期 2000-6-28
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明