利用Blowfish演算法於加密晶片之設計

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姓名

林展瑞(Jan-Ruei Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

利用Blowfish演算法於加密晶片之設計
(Design of Encryption Chips Using the Blowfish Algorithm)

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摘要(中)

本論文提出兩個依據Blowfish演算法為架構的資料加密晶片(BECs)。此兩晶片皆可為微處理器的周邊裝置，也可應用於網路相關產品上。使用者可自定64位元的密鑰，對64位元的資料區塊進行加密或解密的運算，其應用範圍可以包括即時資料傳輸及電子資金轉帳方面。
我們利用VHDL’’87、Synplify 以及Maxplus II 來設計、合成及模擬BECs，最後使用FPGA (Field Programmable Gate Array) 來實現。
第一種為了面積考量所作的設計，其所需logic cell數量為741，最高工作頻率及資料處理量分別約為42.55 MHz和21.28 Mbit/s。第二種為了速度考量所作的設計，其所需logic cell數量為4698，最高工作頻率及資料處理量則分別約為54.9 MHz和43.92 Mbit/s。

摘要(英)

In this thesis, we present two Blowfish encryption chips (BECs) based on the Blowfish algorithm. BECs are microprocessor peripheral devices and might be useful for network devices. They use a 64-bit user-specified key to encrypt and decrypt 64-bit blocks of data. BECs can be used in real time applications and variety of Electronic Funds Transfer applications.
To realize the BECs, we use VHDL’’87, Synplify, and Maxplus; for designing, synthesizing and simulating. Field Programmable Gate Arrays (FPGAs) are chosen as our target hardware environment.
The first design of BEC for area requires 741 logic cells. The maximum operating clock is 42.55 MHz and the corresponding data throughput is about 21.28 Mbit/s. The second design of BEC for speed requires 4698 logic cells. The maximum operating clock is 54.9 MHz and the corresponding data throughput is about 43.92 Mbit/s.

關鍵字(中)

★ 加密晶片
★ 塊狀加密器

關鍵字(英)

★ FPGA
★ blowfish
★ cryptography
★ block cipher

論文目次

CONTENTS
PAGE
ABSTRACT (IN CHINESE) I
ABSTRACT (IN ENGLISH) II
ACKNOWLEDGMENTS III
LIST OF FIGURES IV
LIST OF TABLES VI
CHAPTER 1 INTRODUCTION
1.1Motivation 1
1.2Literature Survey 1
1.3Aim of the Thesis 1
1.4Merit of the Method 2
1.5Organization 2
CHAPTER 2 DESCRIPTION OF BLOWFISH ALGORITHM
2.1 General Description 3
2.2 The Blowfish Cipher 5
2.2.1 Key-expansion Process 5
2.2.2 Data-expansion Process 7
2.2.3 Possible Simplifications 10
2.2.4 Operation Modes of Blowfish 11
2.2.5 Security of Blowfish 14
2.3 Comparisons of Block Ciphers 15
CHAPTER 3 ANALYSIS OF THE BLOWFISH CIPHER MAIN COMPONENTS
3.1 Additions Modulo 2 (XOR) 17
3.2 Additions Modulo 232 on 32-bit Long Words 17
3.3 Key Dependent P-array and S-boxes 19
3.4 The F Function 20
CHAPTER 4 DESIGN OF THE CIPHER ARCHITECTURE
4.1 Blowfish Interface 21
4.1.1 Interface Signals 21
4.1.2 Addressing 22
4.2 Data and Key Flow 23
4.2.1 Design 1 : One-round Implementation 23
4.2.2 Design 2 : Two-round Implementation 26
4.2.3 The Transmission Protocol 27
4.2.4 Operation Sequence 28
4.3 The One-round ALU Circuit 29
4.4 The Two-round ALU Circuit 31
4.5 Control Circuit of the One-round Implementation 33
4.6 Control Circuit of the Two-round Implementation 35
CHAPTER 5 THE RESULTS OF BLOWFISH IMPLEMENTATION USING ALTERA FPGA DEVICES
5.1 Implemented Parts 38
5.2 Implementation of Blowfish Components 39
5.2.1 The F Function 39
5.2.2 One-round ALU 39
5.2.3 Two-round ALU 39
5.3 Implementation of Blowfish Chips 42
5.3.1 One-round Implementation 42
5.3.2 Two-round Implementation 42
5.4 Result and Discussion 55
5.5 Conclusion 56
BIBLIOGRAPHY 57
APPENDIX A) THE DEFAULTS OF P-ARRAY AND S-BOXES 59

參考文獻

BIBLIOGRAPHY
[1]"National Bureau of Standards - Data Encryption Standard," FIPS Publication 46, 1977.
[2]J.-P. Kaps and C. Paar, "Fast DES Implementation for FPGAs and its Application to a Universal Key-search Machine," presented at Workshop in Selected Areas of Cryptography (SAC'98), Kingston, Ont., Aug. 1998.
[3]B. Schneier, "Description of a New Variable-Length Key, 64-Bit Block Cipher (Blowfish)," Fast Software Encryption, Cambridge Security Workshop Proceedings (December 1993), Springer-Verlag, pp. 191-204, 1994.
[4]B. Schneier, "The Blowfish Encryption Algorithm - One Year Later," Dr. Dobb's Journal, September 1995.
[5]B. Schneier, "Applied Cryptography," New York, John Wiley & Sons, 1996.
[6]"National Bureau of Standards - DES Modes of Operation," FIPS Publication 81, 1980.
[7]S. Vaudenay, "Differential Cryptanalysis of Blowfish," unpublished manuscript, 1995.
[8]H. Heys and S. E. Tavares, "Substitution - Permutation Networks Resistant to Differential and Linear Cryptanalysis," Journal of Cryptology, v. 9, n. 1, pp. 1-19, 1996.
[9]H. Heys and S. E. Tavares, "On the Design of Secure Block Ciphers," Proceedings of Queen's 17th Biennial Symposium on Communications, Kingston, Ontario, May 1994.
[10]Altera, "Data Book," 1999.
[11]M. Riaz and H. Heys, "The FPGA Implementation of the RC6 and CAST-256 Encryption Algorithms," in Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering, Edmonton, Alberta, May 1999.
[12]P. Chodowiec and K. Gaj, "Implementation of the Twofish Cipher Using FPGA Devices," Technical Report, July 1999.
[13]D. Honig, "Blowfish Chip Design," unpublished manuscript, Oct. 1997.
[14]Liang-Yu Chang, "Design and Implementation of Data Encryption Processor", Master Thesis, Tatung University, 1997.

指導教授

歐石鏡(Shin-Ching Ou)

審核日期

2000-6-27

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