低複雜度與高速多速率多階有限脈衝響應數位濾波器設計技術

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：10

、訪客IP：18.118.1.158

姓名

林茂青(Maw-Ching Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

低複雜度與高速多速率多階有限脈衝響應數位濾波器設計技術
(Design Techniques for Low-complexity and High-speed Multirate Multistage FIR Digital Filters)

相關論文

★ 應用於2.5G/5GBASE-T乙太網路傳收機之高成本效益迴音消除器	★ 應用於IEEE 802.3bp車用乙太網路之硬決定與軟決定里德所羅門解碼器架構與電路設計
★ 適用於 10GBASE-T 及 IEEE 802.3bz 之高速低密度同位元檢查碼解碼器設計與實現	★ 基於蛙跳演算法及穩定性準則之高成本效益迴音消除器設計
★ 運用改良型混合蛙跳演算法設計之近端串音干擾消除器	★ 運用改良粒子群最佳化演算法之近端串擾消除器電路設計
★ 應用於多兆元網速乙太網路接收機類比迴音消除器之最小均方演算法電路設計	★ 低雜訊輸出緩衝器設計及USB2實體層的傳收器製作
★ 低雜訊輸出緩衝器設計及USB2實體層的時脈回復器製作	★ 應用於通訊系統的內嵌式數位訊號處理器架構
★ 應用於數位儲存示波器之100MHz CMOS 寬頻放大器電路設計	★ 具有QAM/VSB模式的載波及時序回復之數位積體電路設計
★ 應用於通訊系統中數位信號處理器之模組設計	★ 應用於藍芽系統之CMOS射頻前端電路設計
★ 具有QAM/VSB 模式之多重組態可適應性等化器的設計與實現	★ 適用於高速通訊系統之可規劃多模式里德所羅門編解碼模組

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

本論文在提供實現單速率及多速率之低複雜度與高速有限脈衝響應數位濾波器(FIR)時的一些架構性設計的技術與方法，特別是應用在多速率多階內插有限脈衝響應數位濾波器(Interpolated FIR)時之設計上。首先，就一些已知對高速及低功率應用的單速率有限脈衝響應數位濾波器的技術提出概要介紹，接下來提出一些研究的成果，包括可變的濾波器階數的選擇、最佳化的濾波器階數分解和省記憶體及對稱濾波器對等等的技術，可以進一步對多速率多階有限脈衝響應數位濾波器架構獲得性能上的提升與降低其硬體複雜度。然後，基於典型有號數字(CSD)碼及內插有限脈衝響應數位濾波器設計所形成的通用型多速率多階有限脈衝響應數位濾波器將被提出。本論文也介紹一些對高速操作要求的設計，提出既可以增加硬體平行度又可以同時滿足低硬體複雜度的技巧與架構。
一個以TSMC 0.25um CMOS standard cell為製程的64-QAM基頻解調器之濾波器設計實例，證明使用所提出的方法可以將整體使用到的晶片面積減少約39%，適合低複雜度的應用。另外，對於高速的應用，此設計晶片執行速度可高達714MHz。最後，針對CDMA cellular應用的一個降頻8倍之多速率多階無乘法器的降頻器為實例，證明使用所提出的架構與方法可以比傳統方法降低整體晶片面積約70%，同時功率消耗也比使用單階多相位結構傳統方法降低約49%。

摘要(英)

In this thesis, architecture design techniques for implementing single-rate and multirate high-speed finite impulse response (FIR) digital filters, with emphasis on the multirate multistage interpolated FIR (IFIR) digital filters are presented. Well-known techniques to achieve high-speed and low-power applications for the single-rate digital FIR architecture are summarized, followed by the introduction of variable filter order selection, optimal filter decomposition, memory-saving and mirror symmetric filter pairs techniques which offer further gains in both performance and complexity reduction for the multirate multistage digital FIR architecture. Then, a general-purpose multirate multistage digital FIR filter that is based on canonic signed digit (CSD) code representation and IFIR filter design methodology will be proposed. This thesis also describes some techniques by which sufficient parallelism for high-speed operation can be achieved, while simultaneously constraining the solution to have a small hardware implementation for these structures.
A filter design example with TSMC 0.25um standard cell for 64-QAM baseband demodulator shows that the total gate count is reduced by 39% for low-complexity application. Moreover, for high-speed application, the chip can operate at 714MHz. Finally, a multirate multistage multiplierless decimators with decimation factor of eight is designed for the CDMA cellular application. It shows that the total gate count is reduced by 70% as compared with conventional approach. Moreover, the multirate multistage implementation can be reduced by 49% of the power consumption as compared to conventional single-stage implementation with only polyphase structure.

關鍵字(中)

★ 內插有限脈衝響應數位濾波器
★ 有限脈衝響應數位濾波器
★ 典型有號數字碼

關鍵字(英)

★ FIR
★ interpolated FIR
★ CSD code

論文目次

Chapter 1 Introduction
1.1 Introduction........................................................................................1
1.2 Motivation and Goals.........................................................................3
1.3 Thesis Organization............................................................................4
Chapter 2 Design Overview of Multiplierless FIR Digital Filter
2.1 Basic FIR Filter Structures.................................................................7
2.1.1 Direct Form Structure......................................................................8
2.1.2 Transposed Direct Form Structure..................................................9
2.1.3 Linear Phase Transposed Direct Form Structure..........................10
2.2 CSD Multiplier FIR Digital Filter....................................................12
2.2.1 Common Subexpression Elimination..............................................14
2.3 Graph Synthesis Methods.................................................................18
2.4 Basic Multirate Operations...............................................................21
2.4.1 Decimation.....................................................................................21
2.4.2 Interpolation..................................................................................24
2.4.3 The Noble Identities........................................................................26
2.4.4 The Polyphase Representation........................................................27
2.5 Conclusions…………………………………………………………31
Chapter 3 Single-rate FIR Digital Filter Design
3.1 Carry Save Addition.........................................................................33
3.2 Sign Extension Elimination………………………………………...35
3.3 Multiplierless Filter Design……………………………………..….36
3.3.1 CSD Representation.......................................................................37
3.3.2 CSD Multipliers.............................................................................38
3.4 Pipelining..........................................................................................41
3.5 Two-step Local Search Algorithm....................................................43
3.5.1 Scaling Strategy.............................................................................44
3.5.2 Local Search Strategy....................................................................46
3.6 Implementation Structures of FIR Digital Filter...............................46
3.7 Variable Filter Order Selection.........................................................48
3.8 Conclusions…………………………………………………………51
Chapter 4 Multirate FIR Digital Filter Design
4.1 Interpolated FIR Filter Design..........................................................53
4.2 Multirate Multistage Filter Design...................................................58
4.2.1 Interpolated FIR Filter Decomposition........................................60
4.2.2 Multirate Multistage FIR Filter Decomposition..........................65
4.3 Structures of Multirate Multistage FIR Filter...................................67
4.4 Conclusions…………………………………………………………70
Chapter 5 Design and Implementation Examples
5.1 FIR Filter Design..............................................................................71
5.2 Interpolated FIR Filter Design..........................................................75
5.3 Multirate Multistage Filter Design...................................................81
5.3.1 Decimator......................................................................................81
5.3.2 Interpolator....................................................................................83
Chapter 6 Conclusions and Future Works
References.............................................................................................90

參考文獻

[1] B. Porat, “A course in digital signal processing,” John Wiley & Sons, 1997.
[2] P. P. Vaidyanathan, “Multirate systems and filter banks,” Englewood Cliffs, NJ: Prentice Hall, 1993.
[3] R. E. Crochiere and L. R. Rabiner, “Multirate digital signal processing,” Englewood Cliffs, NJ: Prentice Hall, 1983.
[4] Y. Neuvo, C. Y. Dong, and S. K. Mitra, “Interpolated finite impulse response filters,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-32, pp. 563-570, Jun. 1984.
[5] T. Saramäki,Y. Neuvo and S. K. Mitra, “Design of Computationally Efficient Interpolated FIR Filters,” IEEE Trans. Circuits Syst., vol. 35 , no. 1, pp. 563-570, Jan 1988.
[6] G. W. Reitwiesner, “Binary arithmetic,” Advances in Computers, vol. 1, NY: Academic, pp. 231-308, 1966.
[7] N. J. Fliege, “Multirate digital signal processing: multirate systems, filter banks, wavelets,” 1994.
[8] P. Reutz, “The architectures and design of a 20-MHz real-time DSP chip set,” IEEE JSSC, vol. 24, pp. 338-348, Apr. 1989.
[9] H. Samueli, “An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients,” IEEE Trans. Circuits Syst., vol. 36, pp. 1044-1047, Jul. 1989.
[10] Y. C. Lim and S. R. Parker, “FIR filter design over a discrete powers-of-two coefficient space,” IEEE Trans. Acoust., Speech, Signal Processing, vol. 31, pp. 583-591, Jun. 1983.
[11] M. Yagyu, A. Nishihara, and N. Fujii, “Fast FIR digital filter structures using minimal number of adders and its application to filter design,” IEICE Trans. Fundamentals, vol. E79-A, no. 8, pp. 1120-1128, Aug. 1996.
[12] R. Hartley, “Subexpression sharing in filters using canonic signed digit multipliers,” IEEE Trans. Circuits Syst. II, vol. 43, pp. 677-688, Oct. 1996.
[13] M. Potkonjak, M. B. Srivastava, and A. P. Chandrakasan, “Multiple constant multiplications: Efficient and versatile framework and algorithms for exploring common subexpression elimination,” IEEE Trans. Comput.-Aided Design, vol. 15, pp. 151–165, Feb. 1996.
[14] R. Pasko et al., “A new algorithm for elimination of common subexpressions,” IEEE Trans. Comput.-Aided Design, vol. 18, pp. 58–68, Jan. 1999.
[15] H. Safiri, M. Ahmadi, G. A. Jullien, and W. C. Miller, “A new algorithm for the elimination of common subexpressions in hardware implementation of digital filters by using genetic programming,” Proc. IEEE Int. Conf. Application-Specific Systems, Architecture, and Processors, pp. 319–328, July 2000.
[16] Y. Jang and S. Yang, “Low-power CSD linear phase FIR filter structure using vertical common sub-expression,” Electronics Letters, vol. 38, pp. 777-779, July 2002.
[17] A. P. Vinod, E. M-K. Lai, A. B. Premkumar and C. T. Lau, “FIR filter implementation by efficient sharing of horizontal and vertical common subexpressions,” Electronics Letters, vol. 39, pp. 251-253, Jan. 2003.
[18] R. W. Mehler and D. Zhou, “Architectural synthesis of finite impulse response digital filters,” Symp. Integrated Circuits Syst. Design, pp. 20-25, Sep. 2002.
[19] D. R. Bull, “Primitive operator digital filter synthesis using a shift biased algorithm,” in Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, Helsinki, Finland, pp. 1529–1532.
[20] A. Dempster and M. D. Macleod, “Constant integer multiplication using minimum adders,” Proc. Inst. Elec. Eng. Circuits and Systems, vol. 141, no. 5, pp. 407–413, Oct. 1994.
[21] D. R. Bull and D. H. Horrocks, “Primitive operator digital filter,” Proc. Inst. Elec. Eng. Circuits, Devices and Systems, vol. 138, pt. G, pp. 401–412, June 1991.
[22] A. Dempster and M. D. Macleod, “Use of minimum-adder multiplier blocks in FIR digital filters,” IEEE Trans. Circuits Syst. II, vol. 42, pp. 569–577, Sept. 1995.
[23] M. Bellanger, G. Bonnerot, and M. Coudreuse, “Digital filtering by polyphase network: application to sample rate alteration and filter banks,” IEEE Trans. ASSAP, vol. ASSP-24, pp. 109-114, Apr. 1976.
[24] R. A. Hawley, B. C. Wong, T.-J. Lin, J. Laskowski, and H. Samueli, “Design techniques for silicon compiler implementations of high-speed FIR digital filters,” IEEE JSSC, vol. 31, pp. 656-667, May 1996.
[25] K. Y. Jheng, S. J. Jou and A. Y. Wu, “A Design Flow for Multiplierless Linear-Phase FIR Filters from System Specification to Verilog Code,” IEEE International Symposium on Circuits and Systems, vol. 5, pp. 293-296, May 2004.
[26] M. C. Lin, C. L. Chen, D. Y. Hsin, C. H. Lin, and S. J. Jou, “Multiplierless FIR Filter Architecture Synthesizer Based on CSD Code,” Journal of the Chinese Institute of Electrical Engineering, vol. 10, no. 2, pp.155-163, May 2003.
[27] S. J. Jou, S. Y. Wu, and C. K. Wang, “Low-power multirate architecture for IF digital frequency down converter,” IEEE Trans. Circuits Syst. II, vol. 45, pp. 1487-1494, Nov. 1998.
[28] S.-Y. Wu, “Low-power multirate IF digital frequency down converter for wireless communication systems,” MS thesis, Dept. of EE, National Central Univ., Taiwan, Jun. 1997.
[29] I.-C. Park and H.-J. Kang, “Digital filter synthesis based on an algorithm to generate all minimal signed digit representations,” IEEE Trans., CAD of IC and Syst., vol. 21, pp. 1525-1529, Dec. 2002.
[30] B. C. Wong and H. Samueli, “A 200-MHz all-digital QAM modulator and demodulator in 1.2μm CMOS for digital radio applications,” IEEE JSSC, vol. 26, pp. 1970-1979, Dec. 1991.
[31] T.-J. Lin and H. Samueli, “A 200-Mhz CMOS x/sin(x) digital filter for compensating D/A converter frequency response distortion in high-speed communication systems,” IEEE GLOBECOM, vol 3, pp. 1722-1726, Dec. 1990.
[32] R. Jain, P. T. Yang, and T. Yoshino, “FIRGEN: A computer-aided design system for high performance FIR filter integrated circuits,” IEEE Trans. Signal Processing, vol. 39, pp. 1655-1668, Jul. 1991.
[33] R. Hawley, T.-J. Lin, and H. Samueli, “A silicon compiler for high-speed CMOS multirate FIR digital filters,” IEEE Int. Symp. Circuits Syst., vol. 3, pp. 1348-1351, May 1992.
[34] M. Bhattacharya and T. Saramaki, “Some observations on multiplierless implementation of linear phase FIR filters,” IEEE ISCAS, vol. 4, pp. 193-196, May 2003.
[35] G. Jovanovic-Dolecek and S. K. Mitra, “Multiplier-free FIR filter design based on IFIR structure and rounding,” Circuits and Systems, 48th Midwest Symposium on, pp. 559-562, Aug. 2005.
[36] A. Mehrnia and B. Daneshrad, “A low-complexity multirate channel selector transmit filter bank with reconfigurable bandwidth,” Aerospace, IEEE Conference, pp.1739-1749, Mar. 2005.
[37] S. J. Jou, C. H. Kuo, M. T. Shiue, J. Y. Heh and C. K. Wang, “VLSI implementation of timing recovery and carrier recovery for QAM/VSB dual mode,” International Symp. on VLSI Technology, Systems and Applications, Taipei, R. O. C. June 1999, pp.159-162.
[38] “The CDMA network engineering handbook, volume 1: concepts in CDMA,” Qualcomm Inc., Mar. 1993.
[39] M. C. Lin, H. Y. Chen and S. J. Jou, “Design Techniques for High-speed multirate Multistage FIR Digital Filters,” International Journal of Electronics, Vol. 93, No. 10, Oct. 2006, pp.699-721.

指導教授

周世傑、薛木添
(Shyh-Jye Jou、Muh-Tian Shiue)

審核日期

2007-7-5

推文