博碩士論文 88521069 詳細資訊




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姓名 許槐益(Huai-Yi Hsu )  查詢紙本館藏   畢業系所 電機工程研究所
論文名稱 適用於高速通訊系統之可規劃多模式里德所羅門編解碼模組
(Reconfigurable Multi-mode Reed-Solomon Codec for High-Speed Communication Systems)
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摘要(中) 在高速傳輸系統中,里德所羅門碼經常被應用在更正通道所引起的錯誤。對於叢集錯誤(Burst error)與隨機錯誤(Random error),里德所羅門碼可以提供很好的錯誤更正能力,因此成為非常受歡迎的通道編碼方式之一;也因為這個重要的因素,使得里德所羅門碼被應用在許多的傳輸系統上,例如無線通訊系統、纜線數據機(Cable modem)、電腦記憶體、數位用戶迴路(xDSL)等。
在本論文中,我們研究主題落在里德所羅門碼(Reed-Solomon code),並設計一個里德所羅門編解模組(RS codec)的智慧財產(Intelligent Property)。我們的設計主要應用在數位用戶迴路及纜線數據機系統,在這兩者的應用中,系統會偵測傳輸通道的品質,調整適合的規格定義,稱之為多模式系統(multi-mode systems),因此我們提出一個可規劃多模式的里德所羅門碼。此模組包括兩個部份,分別為軟性核心(softcore)和硬體核心(hardcore)。軟性核心為一個可規劃的控制單元,具有可依照系統要求改變規格;而硬體核心為一個固定的資料路徑(datapath),則可最佳化算術單元的執得速度,面積和功率。在實際應用方面,我們可以即時經由控制訊號來重新規劃硬體架構的資料路徑,以達到適用於各種傳輸系統的目的。
在電路實現方面,我們利用平行運算及管線處理的技巧,來達成適用於各種系統應用的可規劃多模式的硬體架構。此晶片採用0.35微米製程,其中包括約34,647個邏輯閘,其核心面積約為1578?微米,在3.3伏特電壓下,其操作頻率可高達100百萬赫茲及功率消耗約為132mW。最後,我們模擬了一些產品應用的系統規格。
摘要(英) In high-speed communication systems, RS codes have a widespread use to provide error protection. For burst errors and random errors, RS code has become a popular choice to provide data integrity due to its good error correction capability. This feature has been an important factor in adopting RS codes in many practical applications such as wireless communication system, cable modem, computer memory, and xDSL systems, etc.
In this thesis, we focus on the topic of Reed-Solomon code, and we develop an Intelligent Property (IP) for RS codec, which includes encoder and decoder. The major issues of our design are focusing on the high-speed communication, which includes the xDSL system and the upstream part of cable modem. According to the characteristics of channel quality, there are different transmission specifications in these two systems. This is called multi-mode system. Therefore, we propose a reconfigurable multi-mode Reed Solomon codec to fit various applications. The codec consists of two parts, the softcore and the hardcore. The part of the softcore is a configurable control unit, which can change RS specification to fit various system application; and the part of the hardcore is a fixed operating datapath architecture, which can optimize the arithmetic units in speed, area, and power. In practical application, we can configure the parameters of RS codec to apply various systems on real-time.
In circuit realization, we use the techniques of parallelism and pipelinism to implement the multi-mode hardcore, which is suitable for applying various systems. The chip is implemented by 0.35 um cell-based technology. The total gate count is about 34,647 and the core size is 1578? um2. The operating frequency is 100MHz, and power consumption is 132mW for 3.3 volt. Finally, we will apply our design to several the specifications of products, e.g., DVD and ADSL systems.
關鍵字(中) ★ 可規劃
★  多模式
★  里德所羅門碼
關鍵字(英) ★ multi-mode
★  reconfigurable
★  RS codec
論文目次 Chapter 1 Introduction1
1.1 Background1
1.2 Motivation2
1.3 Organization6
Chapter 2 Overview of Multi-mode Reed-Solomon Codec8
2.1 Review of Reed-Solomon Code8
2.2 Application of Reed-Solomon Codec10
2.2.1 Reed-Solomon Specification of xDSL System10
2.2.2 Reed-Solomon Specification in Cable System12
2.2.3 Application of Other Systems13
2.3 Specification of Multi-mode Reed-Solomon Codec13
2.3.1 Reconfigurable Part (Softcore)14
2.3.2 Datapath Unit (Hardcore)15
Chapter 3 Datapath Design of Encoder and Decoder of Multi-mode Reed-Solomon Codec17
3.1 Encoder design of Reed-Solomon Codec17
3.1.1 The g(x)-Base Architecture18
3.1.2 The a(x)-Base Architecture19
3.2 Decoder design of Reed-Solomon Codec20
3.2.1 Syndrome Calculation22
3.2.2 Euclidean GCD Algorithm25
3.2.2.1 Euclidean Division Module27
3.2.2.2 Euclidean Multiply Module27
3.2.2.3 Error Magnitude Coefficient Selector28
3.2.3 Chien Search and Forney Algorithm29
3.3 Summary32
Chapter 4 Controller Design of the Configurable Multi-mode Reed-Solomon Codec33
4.1 Parameters of Controller FSM for Multi-mode Reed-Solomon Codec33
4.2 Design of Controller FSM35
4.2.1 Encoding State of Controller FSM36
4.2.2 Decoding State of Controller FSM37
4.2.3 Configurable State of Controller FSM39
Chapter 5 Chip Implementation of Multi-mode Reed-Solomon Codec42
5.1 Design Flow42
5.2 Synthesis and Simulation Results43
5.2.1 Synthesis Results43
5.2.2 Simulation Results45
5.2.2.1 Reed-Solomon Encoding Operation46
5.2.2.2 Reed-Solomon Decoding Operation47
5.3 Chip Summary48
5.4 Comparison of Hardware and Performance50
Chapter 6 Conclusions52
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[2]Wicker and Bhargava, “Reed-Solomon Codes and Their Applications,” IEEE Press, 1994.
[3]S. Whitaker, J. Canaris, and K. Cameron, “Reed-Solomon VLSI codec for advanced television,” IEEE Trans. Circuits System Video Technol., vol. 1, pp. 230-236, June 1991.
[4]I.S. Reed, R. He, X. Chen, and T.K. Truong, “Application of Grobner bases for decoding Reed-Solomon codes used on CDs,” IEE Proceedings-Computers and Digital Techniques, vol. 145, issue. 6, pp. 369-376, Nov. 1998.
[5]H.C. Chang, C.B. Shung, “A (208,192;8) Reed-Solomon decoder for DVD application,” IEEE International Conference, pp. 957-960, vol. 2, 1998.
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[8]Dennis J. Rauschmayer, “ADSL/VDSL Principles: A Pracitical and Precise Study of Asymmetric Digital Subscriber Lines and Very High Speed Digital Subscriber Lines,” Macmillan Technical Publishing, Indianapolis, 1999.
[9]K. Sato, M. Hattori, N. Ohya, and M. Sasano, “ARSDES: An Automated Reed-Solomon Decoder and Encoder Synthesis System,” IEEE Custom Integrated Circuit Conference, pp. 611-614, 1995.
[10]C.L. Shih, “Soft IP Generator of Reed-Solomon Codec for Communication Systems,” Master Thesis, National Central University, 2000.
[11]I.S. Reed and G. Solomon, “Polynomial Codes over Certain Finite Fields,” J. Soc. Ind. Apple. Math. 8,pp. 200-204, June 1860.
[12]Stephen B. Wicker, “Error Control Systems for Digital Communication and Storage,” Prentice Hall, 1995.
[13]G. Fettweis, M. Hassner, “A Combine Reed-Solomon Encoder and Syndrome Generator with Small Hardware Complexity,” Circuits and Systems, ISCAS 92 Proceedings, vol. 4, pp. 1871-1874, 1992.
[14]A. Raghupathy; K.J.R. Liu, “Algorithm-based low-power/high-speed Reed Solomon decoder design,” IEEE Transactions on Circuits and Systems II, Vol. 47, Issue: 11, pp. 1254 —1270, 2000.
[15]R. Blahut, “Theory and Practice of Error Control Codes,” Addison-Wesley Co., 1983.
[16]H. Lee, M.L. Yu, and L. Song, “VLSI Design of Reed-Solomon Decoder Architecture,” ISCAS 2000 Proceedings Circuits and Systems, pp. v-705-708, 2000.
[17]H.M. Shao, T.K. Truong, L.J. Deutsch, J.H. Yuen, I.S. Reed, “A VLSI Design of a Pipeline Reed-Solomon Decoder,” IEEE Trans. on Computers, vol. C-34, no. 5, May 1985.
[18]Po Tong, “A 40-Mhz Encoder-Decoder Chip Generated by a Reed-Solomon Code Compiler,” IEEE 1999 Proceedings, Custom Integrated Circuits Conference. pp. 13.5/1 -13.5/4, 1990.
[19]S. Kwon, H. Shin, “An Area-efficient VLSI Architecture of a Reed-Solomon Decoder/Encoder for Digital VCRS,” IEEE Trans on Consumer Electronics, vol. 43, no. 4, Nov 1997.
[20]J. C. Huang, C. M. Wu, M. D. Shieh, and C. H Wu, “An Area-Efficient Versatile Reed-Solomon Decoder for ADSL,” Circuits and Systems, 1999. ISCAS '99, pp. 517-520, vol. 1, 1999.
指導教授 周世傑(Shyh-Jye Jou) 審核日期 2001-6-26
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