||In high-speed communication systems, RS codes have a widespread use to provide error protection. For burst errors and random errors, RS code has become a popular choice to provide data integrity due to its good error correction capability. This feature has been an important factor in adopting RS codes in many practical applications such as wireless communication system, cable modem, computer memory, and xDSL systems, etc.|
In this thesis, we focus on the topic of Reed-Solomon code, and we develop an Intelligent Property (IP) for RS codec, which includes encoder and decoder. The major issues of our design are focusing on the high-speed communication, which includes the xDSL system and the upstream part of cable modem. According to the characteristics of channel quality, there are different transmission specifications in these two systems. This is called multi-mode system. Therefore, we propose a reconfigurable multi-mode Reed Solomon codec to fit various applications. The codec consists of two parts, the softcore and the hardcore. The part of the softcore is a configurable control unit, which can change RS specification to fit various system application; and the part of the hardcore is a fixed operating datapath architecture, which can optimize the arithmetic units in speed, area, and power. In practical application, we can configure the parameters of RS codec to apply various systems on real-time.
In circuit realization, we use the techniques of parallelism and pipelinism to implement the multi-mode hardcore, which is suitable for applying various systems. The chip is implemented by 0.35 um cell-based technology. The total gate count is about 34,647 and the core size is 1578? um2. The operating frequency is 100MHz, and power consumption is 132mW for 3.3 volt. Finally, we will apply our design to several the specifications of products, e.g., DVD and ADSL systems.
||S. Lin and D. J. Costello, Jr., “Error Control Coding: Fundamentals and Applications,” Englewood Cliffs, NJ: Prentice-Hall, 1983. |
Wicker and Bhargava, “Reed-Solomon Codes and Their Applications,” IEEE Press, 1994.
S. Whitaker, J. Canaris, and K. Cameron, “Reed-Solomon VLSI codec for advanced television,” IEEE Trans. Circuits System Video Technol., vol. 1, pp. 230-236, June 1991.
I.S. Reed, R. He, X. Chen, and T.K. Truong, “Application of Grobner bases for decoding Reed-Solomon codes used on CDs,” IEE Proceedings-Computers and Digital Techniques, vol. 145, issue. 6, pp. 369-376, Nov. 1998.
H.C. Chang, C.B. Shung, “A (208,192;8) Reed-Solomon decoder for DVD application,” IEEE International Conference, pp. 957-960, vol. 2, 1998.
“Annex B to ITU-T Recommendation J.83, Digital multi-programme systems for television sound and data services for cable distribution,” Oct. 1995.
Walter Y. Chen, “DSL: Simulation Techniques and Standards Development for Digital Subscriber Line Systems,” Macmillan Technical Publishing, Indianapolis, 1998.
Dennis J. Rauschmayer, “ADSL/VDSL Principles: A Pracitical and Precise Study of Asymmetric Digital Subscriber Lines and Very High Speed Digital Subscriber Lines,” Macmillan Technical Publishing, Indianapolis, 1999.
K. Sato, M. Hattori, N. Ohya, and M. Sasano, “ARSDES: An Automated Reed-Solomon Decoder and Encoder Synthesis System,” IEEE Custom Integrated Circuit Conference, pp. 611-614, 1995.
C.L. Shih, “Soft IP Generator of Reed-Solomon Codec for Communication Systems,” Master Thesis, National Central University, 2000.
I.S. Reed and G. Solomon, “Polynomial Codes over Certain Finite Fields,” J. Soc. Ind. Apple. Math. 8,pp. 200-204, June 1860.
Stephen B. Wicker, “Error Control Systems for Digital Communication and Storage,” Prentice Hall, 1995.
G. Fettweis, M. Hassner, “A Combine Reed-Solomon Encoder and Syndrome Generator with Small Hardware Complexity,” Circuits and Systems, ISCAS 92 Proceedings, vol. 4, pp. 1871-1874, 1992.
A. Raghupathy; K.J.R. Liu, “Algorithm-based low-power/high-speed Reed Solomon decoder design,” IEEE Transactions on Circuits and Systems II, Vol. 47, Issue: 11, pp. 1254 —1270, 2000.
R. Blahut, “Theory and Practice of Error Control Codes,” Addison-Wesley Co., 1983.
H. Lee, M.L. Yu, and L. Song, “VLSI Design of Reed-Solomon Decoder Architecture,” ISCAS 2000 Proceedings Circuits and Systems, pp. v-705-708, 2000.
H.M. Shao, T.K. Truong, L.J. Deutsch, J.H. Yuen, I.S. Reed, “A VLSI Design of a Pipeline Reed-Solomon Decoder,” IEEE Trans. on Computers, vol. C-34, no. 5, May 1985.
Po Tong, “A 40-Mhz Encoder-Decoder Chip Generated by a Reed-Solomon Code Compiler,” IEEE 1999 Proceedings, Custom Integrated Circuits Conference. pp. 13.5/1 -13.5/4, 1990.
S. Kwon, H. Shin, “An Area-efficient VLSI Architecture of a Reed-Solomon Decoder/Encoder for Digital VCRS,” IEEE Trans on Consumer Electronics, vol. 43, no. 4, Nov 1997.
J. C. Huang, C. M. Wu, M. D. Shieh, and C. H Wu, “An Area-Efficient Versatile Reed-Solomon Decoder for ADSL,” Circuits and Systems, 1999. ISCAS '99, pp. 517-520, vol. 1, 1999.