應用於ATSC VSB時脈回復之全數位延遲線迴路

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姓名

胡嘉琳(Chia-Lin Hu ) 查詢紙本館藏

畢業系所

電機工程研究所

論文名稱

應用於ATSC VSB時脈回復之全數位延遲線迴路
(All Digital DLL for ATSC VSB Timing Recovery)

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摘要(中)

在此主要的研究目標是設計一適用於ATSC VSB時脈回復電路之全數位延遲線迴路。此電路有幾個特點 : 第一、整個電路為全數位化，可直接使用硬體語言(Verilog) 描述其功能，且使用自動化佈局工具實現。第二、此電路的主要架構為一串128級的反相器，非常簡單，所佔的面積很小。第三、其偵測電路只有一個D型正反器判斷相位的領先或落後，此方式也很簡易且判斷速度符合規格要求。第四、為了增加迴路對時脈抖動的抵抗能力，我們加上一個信心計數器來確定偵測電路所判斷的值。第五、使用有限狀態機 (finite state machine) 控制整個迴路。
我們透過C和Verilog的模擬驗證其可行性，且使用TSMC 0.35μm 1P4M的製成實現整個硬體架構。整個電路只使用了近3000個邏輯閘，晶片面積為524μm×517μm (不包含I/O 單元) 。晶片測試結果也符合規格的要求，其所能產生之相位解析度為370ps至810ps之間，時脈所產生之抖動在270ps之內。

摘要(英)

In this thesis, an all-digital delay locked loop for ATSC VSB timing recovery has been proposed and implemented. The proposed architecture has the following distinguishing features. First, the all the circuit is digitalized. Its functions have been described by hardware description language (Verilog). Auto place and route tool are used to implement the circuit. Second, the main structure of this circuit is a string of 128 inverters. It is very simple to accomplish and the area is small. Third, it uses only the lead-lag decision for the DLL instead of the phase difference information for the DLL to minimize the hardware complexity. Forth, it takes the confidence counter to improve the stability against the clock jitter and environment noise. Fifth, it uses the finite state machine to control the whole circuit.
We use C language and Verilog language to simulate the architecture and verify the functionality. Then, the chip had been designed and implemented using TSMC 0.35μm 1P4M technology. The gate count of 3000 reconfirms the simplicity of the architecture. The area of the chip is 524μm×517μm (not including I/O pad). Finally, the test result fits the required specification It products a phase resolution between 370ps to 810ps, and the clock jitter is lower than 270

關鍵字(中)

★ 延遲線迴路
★ 時脈回復

關鍵字(英)

★ DLL
★ Timing Recovery

論文目次

Chapter 1Introduction
1.1Overview
1.2Introduction of ATSC HDTV System
1.3Survey of the Timing Recovery Architecture
1.4Motivation
1.5Introduction of DLL
1.6Survey of the Delay Locked Loop
1.7Thesis Organization
Chapter 2 Architecture
2.1Overview
2.2Tap Delay Line , Switch, and Multiplexer
2.3Lead/Lag Detection
2.4Align_state Block
2.5Pasecomp_state Block
Chapter 3 Design Considerations
3.1Phase resolution
3.2Analyze the phase resolution
3.3The relationship between phase resolution and confidence counter
3.4The clock jitter propagation
Chapter 4Implementation and simulation result
4.1C program simulation result
4.2Verilog simulation result
4.3Design Analyzer simulation result
4.4Chip Implementation
4.5Post layout simulation result
Chapter 5Test consideration and result
5.1Test consideration
5.2Test method
5.3Test result
Chapter 6The application of DLL on ATSC HDTV timing recovery
6.1Overview
6.2C program simulation and result
Chapter 7Conclusion
Bibliography

參考文獻

[1]Advanced Television System Committee, ATSC Digital Television Standards, Sept. 1995.
[2]Advanced Television System Committee, Guide to the use of ATSC Digital Television Standards, Oct. 1995.
[3]Gary Sgrignili, Wayne Bretl, and Richard Citta, “VSB Modulation Used for Terrestrial and Cable Broadcasts”, IEEE Trans. On Consumer Electronics, Vol. 42, No. 3, Aug. 1995, pp.367-382.
[4]Kim, Shin, and Song, “A Symbol Timing Recovery Using the Segment Sync Data for the Digital HDTV GA VSB System”, IEEE Tran. On Consumer Electronics, Vol. 42, No. 3, August 1996, pp.651-656.
[5]C.C. Su, L.Y. Huang, J.J. Lee, and C.K. Wang, “A Frame-Based Symbol Timing Recovery for Large Pull-in Rang and Small Steady Sate Variation,” Proc. 1999 Asia Pacific Conference on ASICs, 1999, pp. 75-78.
[6]Ting-Yuan Cheng, “Immediately Frequency and Phase Error Compensation Technique for the Frame Based Timing Recovery”, Master Thesis, NCU Department of Electrical EngineeringNational Central UniversityChung-Li, ROC, 1999.
[7]Roland E. Best, “Phase-Locked Loops: Theory, Design, and Applications”, McGraw-Hill Inc., 2nd ed., 1993.
[8]Stefnos Sidiropouls, and Mark A, Horowits, “A Semidigital Dual Delay-Locked Loop”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 32, NO. 11, November 1997, pp. 1683-1692.
[9]Bruno W. Garlepp, Kevin S. Donnely, et al., “A Portable Digital DLL for High-Speed CMOS Interface Circuits”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 34, NO. 5, MAY 1999, pp. 632-644.
[10]Thomas H. Lee, Kevin S, Donnelly, John T. C. Ho, Jared Zerbe, Mark G. Johnson, and Toru Ishikawa, “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 29, NO. 12, December 1994, pp.1491-1496.

指導教授

蘇朝琴(Chauchin Su)

審核日期

2001-6-30

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