博碩士論文 88521072 詳細資訊




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姓名 陳怡廷(Yi-Ting Chen )  查詢紙本館藏   畢業系所 電機工程研究所
論文名稱 適用於通訊系統的內嵌式數位信號模組設計
(The Data Path of Embedded DSP Architecturefor Communication Application)
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摘要(中) 本篇論文介紹一個為內嵌式系統設計的可程式化數位信號處理器( Digital Signal Processor )的架構與資料通路( data path )。為了符合各種不同內嵌式系統的需求,於是我們提出有彈性而且低功率的數位訊號處理器。
這個可參數化的數位訊號處理器有不同獨立的參數可以設定。我們更進一步地加入一些特殊應用於通訊系統的電路給使用者選用。我們把這一種處理器稱為可參數化融合特殊應用於數位訊號基礎的處理器 ( parameterized ASIC/DSP processor )。除了特殊應用的電路外,為了增強整體的效能,我們加入高度平行化的架構稱之為雙 MAC 架構。最後,為了減少功率消耗,我們也應用了一個低功率的 MAC 單元在這顆數位訊號處理器裡。
摘要(英) This thesis introduces the architecture and data path of a programmable DSP processor designed for embedded system. To meet the various embedded system needs, a flexible and low power DSP core is proposed.
The proposed DSP processor itself is a parameterized core with several independent parameters. Furthermore, a better concept is to combine some special-purposed circuits in the parameterized DSP core for option. And we term this kind processor as parameterized ASIC/DSP processor. In addition to the special-purposed circuits, the highly degree parallelism architecture ( Dual MAC ) is used in the processor to upgrade its performance. In order to reduce the power consumption, a low power MAC unit is used in the DSP
關鍵字(中) ★ 數位訊號處理器
★  資料通路
關鍵字(英) ★ data path
★  DSP processor
論文目次 Contents
Chapter 1Introduction1
1.1Motivation1
1.2Evolution of Communication DSP Processors3
1.3Applications-Specific DSP For Communication and Embedded system4
1.4Thesis Organization6
Chapter 2Overall Architecture7
2.1Introduction7
2.2The Memory Architecture of NCU_DSP7
2.3The Address mode used in NCU_DSP9
2.4The Modified Data Path11
2.5The Pipeline stage of NCU_DSP:13
2.6Parameterized DSP Core14
2.7Summary15
Chapter 3The Design of Data Path16
3.1Introduction16
3.2Status register17
3.340-bit Arithmetic Logic Unit18
3.3.1Sign Extension Mode19
3.3.2Saturation and Overflow19
3.3.3Rounding21
3.4Accumulators22
3.5Shifter23
3.6Multiply-Accumulate Unit24
3.6.1Fractional/Integer Multiplication:26
3.6.2Low Power Scheme in Multiplier27
3.6.3Low Power MAC Unit30
3.7Pipeline stage32
Chapter 4I/O Design for Embedded DSP34
4.1Introduction34
4.2The Profile of Host Port Interface ( HPI )34
4.3Handshaking Mode37
4.3.1The Detail Block Diagram of Handshaking Mode38
4.3.2The Timing of Transmission41
4.3.3Example of Access Sequences41
4.4Direct Memory Access mode43
4.4.1IP Considerations43
4.4.2The Architecture of DMA Mode44
4.4.3The Timing Diagram of Transmission48
4.4.4Example of Access Sequence49
4.5Merge Mode50
4.5.1The Architecture of Merge Mode50
4.6Summary52
Chapter 5Parameterized Modules53
5.1Introduction53
5.2Parameterized & Configurable Architecture53
5.3Hamming Distance Calculator Block55
5.4The Sub-Word Multiplier57
5.5The Dedicated FIR Generator58
5.6Multi-Level Slicer59
5.7The Overhead of Special Units60
5.8Summary61
Chapter 6Chip Implementation62
6.1Introduction62
6.1.1Gate Level Timing Simulation Result62
6.1.2Gate Level Area Simulation Result63
6.1.3Layout View64
6.2Test Consideration66
6.3Benchmarks67
Chapter 7Conclusions70
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[3]I. Verbauwhede and M. Touriguian, "A low power DSP engine for wireless communications," Journal of VLSI Signal Processing Systems, vol. 18, no.2, Feb. 1998
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[8]V. K. Madisetti, “VLSI Digital Signal Processors: An Introduction to Rapid Prototyping and Design Synthesis,” Butterworth-Heinemann Publishers, 1995.
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[10]E. A. Lee, “Programmable DSP Architectures: Part II,” IEEE ASSP Magazine, pp. 4-14, January, 1989.
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[12]“TMS320C54X DSP Reference Set: Volume 1: CPU and Peripherals,” Texas Instruments, 1997.
[13]P. Lapsley, J. Bier, A. Shoham, E. A. Lee, “DSP Processor Fundamentals,” IEEE Press, 1997.
[14]K. Hwang, Computer Arithmetic Principles, Architecture, and Design, John Wiley & Sons, 1979
[15]Rafael Fried, ”Minimizing Energy Dissipation in High-Speed Multipliers,” IEEE International Symposium on Low Power Electronics and Design, pp214-219, 1997.
[16]E. de Angel and E.E. Swartzlander, ”Low Power Parallel Multipliers,” VLSI Signal Processing, IX, pp.199-208, 1996.
[17]The TMS320C54c DSP HPI and PC parallel Port Interface Application Report, 1997
[18]M. M. Mano, C. R. Kime, “Logic and Computer Design Fundamentals,” Prentice-Hall Publishers, 1997.
[19]J. Hennessy, D. Patterson, “Computer Organization & Design: The Hardware/Software Interface,” 2 nd edition, Morgan Kaufmann Publishers, 1998.
[20]M. Keating, P. Bricaud “REUSE MATHODOLOGY MANUAL FOR SYSTEM-ON-A-CHIP DESIGNS” 2 nd edition, Kluwer Academic Pblshers, 1999.
[21]A. Gierlinger, R. Forsyth, E. Ofner, “Gepard: A Parameterisable DSP Core for ASICS,” ICSPAT, pp. 203-207, 1997.
[22]M. Dolle, M. Schlett, “ A Cost-Effective RISC/DSP Microprocessor for Embedded Systems,” IEEE Micro, pp.32-40,1995.
[23]J. Warden, “ Sub-Word Parallelism in Digital Signal Processing,” IEEE Signal Processing Magazine, March, pp.27-35, 2000.
[24]H. H. Wang, “Module Design of DSP Core for Communication System,” Dep. Elec. Eng., National Central University, Taiwan, June, 2000.
[25]C. L. Chen,“FIR Architecture Synthesizer Based on CSD Code,” Dep. Elec. Eng., National Central University, Taiwan, June, 1998.
[26]H.P. Lee, "Embedded DSP Core for Communication System," Dep. Elec. Eng., National Central University, Taiwan, June,2001
指導教授 周世傑(Shyh-Jye Jou) 審核日期 2001-7-9
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