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姓名 郭俊誠(Chun-Cheng Kuo ) 查詢紙本館藏 畢業系所 電機工程研究所 論文名稱 超取樣技巧之資料回復系統及USB2之應用
(Data Recovery Using Oversampling Technique and Its Application in USB2)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 近年來，因為多媒體的應用，資料的傳輸量越來越大，而在傳輸的介質上又以便宜的序列匯流排為主要的傳輸介質，所以如何以有限的傳輸線去傳最多的資料是一個很重要的課題，這對接收端的資料回復(Data Recovery)系統也同樣是一個很大的考驗，傳統上以鎖相迴路(Phase Locked Loop)架構完成的資料回復系統會受到製程的限制以致於不適合在高速上的應用。
本論文中，我們以萬用串連匯流排(Universal Serial Bus, USB)的高速模式480Mb/s做為我們應用的目標。接下來會對資料回復的一些概略性的介紹。我們選擇整合度高的CMOS而不考慮其他較高速如：GaAs, BiCMOS的製程來完成資料回復電路。最後選擇以超取樣的電路架構來實現USB的資料回復系統。我們提出了一個解決發射端與接收端頻率誤差造成underflow與overflow問題的彈性緩衝(elastically buffer)電路，其規律的架構可以對硬體實現上有很大的幫助，所需的緩衝大小及延遲時間關係也予以推導。整個電路將以tSMC 0.35um 1P4M的數位製程予以實現。整個電路可以工作到625MHz而且可以處理15位元的overflow或是16位元的underflow。摘要(英) Recently, because of the multimedia applications the bandwidth requirement is increased. The serial bus is primary transmission media result in cost. How to transmit the most data in the limited channel becomes a great problem. Data recovery in the receiver also faces this problem. The traditional Phase Locked Loop based data recovery is not suitable for high-speed applications because of the process limitation.
In this thesis, we will implement the high-speed mode data recovery of Universal Serial Bus and its speed is up to 480Mb/s. The concept of the data recovery will be introduce first. We choose CMOS process for its better integrity than GaAs and BiCMOS. Final the data recovery of the USB uses the oversampling circuit architecture. We proposed the elastically buffer architecture used to handle the underflow or overflow problem, which is caused by the frequency offset of transmitter and receiver. Its regular architecture is helpful in hardware implementation. The relationship of the buffer size and latency is also provided. The overall circuits implement in tSMC 0.35um 1P4M digital process. The performance of the data recovery can reach 625MHz and 15 bits overflow or 16 bits underflow can be deal with.關鍵字(中) ★ 序列
★ 萬用序列匯流排
★ 資料回覆
★ 超取樣
★ 高速關鍵字(英) ★ data recovery
★ high speed
★ link
★ oversampling
★ USB論文目次 Chapter 1 Introduction1
1.1Introduction of High-Speed Link1
1.2Motivation2
1.3Thesis Organization4
Chapter 2 Overview of USB2 Specifications5
2.1Introduction5
2.1.1USB2 System Description6
2.1.2USB2 Physical Interface7
2.1.3Overview of USB2 Transceiver8
2.2Specification of USB2 Data Recovery9
2.3Summary11
Chapter 3 Data Recovery12
3.1Introduction12
3.2Clock and Timing Recovery12
3.3Serial Link Transceiver Architecture15
3.3.1Clock Recovery using PLL18
3.3.2Data Recovery using Oversampling19
3.4Summary21
Chapter 4 Oversampling Circuit Design22
4.1Introduction22
4.2Oversampling Design Problem23
4.2.1Initial Synchronization23
4.2.2Frequency Offset24
4.3Oversampling Ratio25
4.4Oversampling Design Techniques27
4.4.13-phase DLL28
4.4.2Sampling Block29
4.4.3Sliding Window29
4.4.4Transition Detector and Optimal Phase Decision30
4.4.5Center Peaking and Majority Vote32
4.4.6Elastically Buffer33
4.4.7Preamble40
4.4.8Timing of Overall Design41
4.5Simulation Results42
4.6Implementation Results43
4.7Test Consideration46
4.8Summary47
Chapter 5 Oversampling Circuits in High Speed System48
5.1Introduction48
5.2Differential Current Switch Logic48
5.3Oversampler51
Chapter 6 Conclusions54參考文獻 [1] Chih-Kong Ken Yang, F. R. Ramin and M.A. Horowitz, “A 0.5-/spl mu/m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling Solid-State Circuits,” IEEE J. Solid-State Circuits, vol.33, No.5, pp.713 —722, May. 1998.
[2] Chih-Kong Ken Yang and M.A. Horowitz, “A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links,” IEEE J. Solid-State Circuits, vol.31, No.12, pp.2015 —2023, Dec. 1996.
[3] K. Lee, S. Kim, G. Ahn and D. K. Jeong, “A CMOS serial link for fully duplexed data communication,” IEEE J. Solid-State Circuits, vol.30, No.4, pp.353 —364, April. 1995.
[4] S. Kim, K. Lee, D. K. Jeong, D. D. Lee and A.G. Nowatzyk, “An 800 Mbps multi-channel CMOS serial link with 3/spl times/ oversampling,” Custom Integrated Circuits Conference, 1995, pp.451 —455.
[5] USB Implementers Forum web page at http://www.usb.org.
[6] R. D. Chiao, “The Low Noise Output Buffer Design Techniques and Clock Recovery Implementation for USB2 Physcial Layer,” M.S. dissertation, Dep. Elec. Eng., National Central University, Taiwan, May 2000.
[7] S. H. Kuo, “The Low Noise Output Buffer Design Techniques and Transceiver Implementation for USB2 Physical Layer,” M.S. dissertation, Dep. Elec. Eng., National Central University, Taiwan, May 2000.
[8] M. C. Chang, “The Design and Application of Self-Biased Delay-Locked Loop,” M.S. dissertation, Dep. Elec. Eng., National Central University, Taiwan, June 1999.
[9] Universal Serial Bus specification revision 2.0, Mar. 2000.
[10] K. Lee, Y. Shin, S. Kim, D. K. Jeong, G. Kim, B. Kim and D. V. Costa, “1.04 GBd low EMI digital video interface system using small swing serial link technique,” IEEE J. Solid-State Circuits, vol.33, No.5, pp.816 —823, May. 1998.
[11] M. Fukaishi, K. Nakamura, M. Sato, Y. Tsutsui, S. Kishi and M. Yotsuyanagi, “A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture,” IEEE J. Solid-State Circuits, vol.33, No.12, pp.2139 —2147, Dec. 1998.
[12] B. Sklar, Digital Communications, Englewood Cliffs, PTR Prentice Hall, 1998
[13] D. Somasekhar and K. Roy, “Differential current switch logic: a low power DCVS logic family,” IEEE J. Solid-State Circuits, vol.31, No.7, pp.981 —991, July. 1996.
[14] IEEE Std 1394b-2000: IEEE standard for a high perf
[15] RAMBus specification Version 1.11, July. 2000
[16] IEEE Std 803.2: IEEE standard for 1000Mbps Ethernet指導教授 周世傑(Shyh-Jye Jou) 審核日期 2001-6-21 推文 plurk
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