博碩士論文 88521084 詳細資訊




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姓名 王偉州(Wei-Juo Wang )  查詢紙本館藏   畢業系所 電機工程研究所
論文名稱 高準確度及低成本之電壓量測技術
(High Precision and Low Cost Voltage Metrology)
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摘要(中) 近年來由於混合信號量測的需求遽增,加上單晶片系統 (System on chip)技術的快速發展,使得晶片容量越來越大,於是就需要快速且多針腳的測試機台來滿足日益嚴苛的測試規格要求。因此,如何能準確且快速的量測信號,儼然已成了一項複雜且困難的事。
在這個論文中,我們提出一個方法來準確的量測電壓。此一技術將可使用於PE IC 中的比較電路,以較為簡單的方法來量測。除此之外,我們會用機率與統計的數學觀點分析此方法的可行性,並推導在雜訊嚴重影響的環境下,如何得到較為準確的量測資料。除了有理論的推導證明之外,我們也會利用硬體的實作與實測以驗證此方法的可行性。
摘要(英) In recent years, the demand of mixed signal testing and fast development of system on chip technology are high due to the size of the chip grows larger and larger. However, faster and more complex test equipments are needed to meet the much demanding test specifications. Thus, test the chip precisely and efficiently becomes a difficult and more complicated task.
In this thesis, we propose a new methodology to measure voltage precisely. The method is able to utilize the comparators in Pin Electronic ICs to exercise the measurement task. The proposed technique simplifies the DAC or LCD Driver IC measurement significantly. Here, we use the probability and statistic methods to analyze the proposed methodology. Experimental results using a demo circuit and a vendor PE card have verify and confirm the feasibility of the proposed methodology.
關鍵字(中) ★ 前端驅動電路
★  數位類比轉換器測試
★  比較器
★  準確度
★  電壓量測
關鍵字(英) ★ comparator
★  DAC test
★  Pin Electronic circuit
★  pricise
★  voltage measurment
論文目次 Chapter 1 Introduction4
1.1Motivation4
1.2Thesis Organization3
Chapter 2 Voltage Measurement Survey and Application Overview4
2.1Introduction4
2.1PMU5
2.2DAC Fault Model and Its Testing6
2.3DAC testing methods10
2.4PE card13
2.5LCD driver14
2.6IEEE 1149.4 internal test19
Chapter 3 System Architecture and Test Methodology21
3.1Introduction21
3.2System Block Diagram22
3.3Probability Derivation23
3.4Confidence Level and Sampling Points27
3.5Boundary Problem30
3.6Obtain Voltage Level32
3.7Summary35
Chapter 4 Simulation Results and Hardware Implementation36
4.1Introduction36
4.2Software simulation and verification36
4.3Hardware implementation and verification40
4.4Compare and analyze the data51
Chapter 5 Conclusion58
參考文獻 [1]Mark Burns, Gordon W. Roberts “An introduction to Mixed-Signal IC test and Measurement”, OXFORD UNIVERSITY PRESS 2001.
[2]Arabi K, Kaminska B, Rzeszut J. “BIST for D/A and A/D converters”, IEEE Design & Test of Computers, Volume: 13 Issue: 4, winter 1996 Page(s): 40 —49.
[3]Arabi, K, “A built-in self-test approach for medium to high-resolution digital-to-analog converters” Test Symposium, 1994, Proceedings of the Third Asian, 1994 Page(s): 373 —378.
[4]Hassan, I.H.S.; Arabi, K.; Kaminska, B. “Testing digital to analog converters based on oscillation-test strategy using sigma-delta modulation” VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on , 1998 , Page(s): 40 —46.
[5]Donald F, Murrray C, Michael Nash, “Critical parameters for high-performance dynamic response measurements” International test conference 1990, page(s): 462-471.
[6]Branson, C.W. “Integrating tester pin electronics” IEEE Design & Test of Computers, Volume: 7 Issue: 2 , April 1990 Page(s): 4 —14
[7]Gasbarro, J.A.; Horowitz, M.A. “Integrated pin electronics for VLSI functional testers” Custom Integrated Circuits Conference, 1988, Proceedings of the IEEE 1988 , 1988 Page(s): 16.2/1 -16.2/4
[8]Itakura, T, “Effects of the sampling pulse width on the frequency characteristics of a sample-and-hold circuit” Circuits, Devices and Systems, IEE Proceedings- Volume: 141 4 , Aug. 1994 , Page(s): 328 —336
[9]De Rycke, I.; De Baets, J.; Doutreloigne, J.; Van Calster, A.; Vanfleteren, J. “The realisation and evaluation of poly-CdSe TFT driving circuits” Display Research Conference, 1988., Conference Record of the 1988 International , 1988 Page(s): 70 —73
[10]Lo, W.M.; Kung, A.; Chan, Y.; Wong, V.W.S. “LCD Driver Design For Mobile Communications System” Information Display, 1997, Proceedings of the Fourth Asian Symposium on Page(s): 91 —97
[11]Valencic, V.; Ballan, H.; Deval, P.; Hochet, B.; Declercq, M. “50-V LCD driver integrated in standard 5-V CMOS process” Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994 , 1994 Page(s): 578 —581
[12]Byong-Deok Choi; Heuisung Jang; Oh-Kyong Kwon; Hong-Gyu Kim; Myung-Jin Soh, “Design of poly-Si TFT-LCD panel with integrated driver circuits for an HDTV/XGA projection system” Consumer Electronics, IEEE Transactions on , Volume: 46 Issue: 1 , Feb. 2000 Page(s): 95 —104
[13]Mahoney, A.W.; Doyle, F.J., III; Ramkrishna, D, “Inverse problem approach to modeling of particulate systems” American Control Conference, 2000. Proceedings of the 2000, Volume: 3 , 2000 Page(s): 1727 -1731 vol.3
[14]Shima, T.; Itakura, T.; Yamada, S.; Minamizaki, H.; Ishioka, T, “Principle and applications of an autocharge-compensated sample and hold circuit” Solid-State Circuits, IEEE Journal of , Volume: 30 Issue: 8 , Aug. 1995 Page(s): 906 —912
[15]Shima, T.; Itakura, T.; Minamizaki, H.; Yagi, T.; Maruyama, T, “TFT-LCD panel driver IC using dynamic function shuffling technique” Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International , 1997 Page(s): 192 -193, 455
[16]Watanabe, A.; Maekawa, M.; Hamada, M.; Hirase, J , ”High precision testing method of mixed signal device” Instrumentation and Measurement Technology Conference, 1994. IMTC/94. Conference Proceedings. 10th Anniversary. Advanced Technologies in I & M., 1994 IEEE, 1994 Page(s): 1284 -1288 vol.3
[17]Chua-Chin Wang, Chi-Feng Wu, Sheng-Hua Chen; Chia-Hsiung Kao “In-sawing-lane multi-level BIST for known good dies of LCD drivers” Electronics Letters, Volume: 35 Issue: 18 , 2 Sept. 1999 Page(s): 1543 —1544
[18]Kac, U.; Novak, F.; Macek, S.; Zarnik, M.S. “Alternative test methods using IEEE 1149.4” Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings, 2000 Page(s): 463 —467
[19]“IEEE standard for a mixed-signal test bus” , IEEE Std 1149.4-1999 , 28 March 2000
指導教授 蘇朝琴(Chauchin Su) 審核日期 2001-6-29
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