博碩士論文 88521085 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:9 、訪客IP:3.92.28.84
姓名 陳俊宏(Jun-Hong Chen )  查詢紙本館藏   畢業系所 電機工程研究所
論文名稱 內建式類比數位/數位類比轉換器線性度之自我測試
(BIST for ADCs/DACs Linearity Testing)
相關論文
★ 匯流排上的時間延遲及交談失真的偵錯設計技巧★ 適用於自動測試機台的時間產生器
★ 混波測試匯流排的量測學★ 高速連結之時序與資料回復
★ 基於IEEE 1057之類比數位轉換器量測技術★ 應用於高畫質電視之載波回復電路架構
★ 單晶片測試機之前端驅動電路設計★ 系統晶片類比數位轉換器測試之數位信號處理程式庫
★ A 2.5V,0.35um,2.5Gbps 傳送接收器設計★ 高準確度及低成本之電壓量測技術
★ 應用於ATSC VSB時脈回復之全數位延遲線迴路★ 適用於晶片間通訊之高速傳輸介面
★ 內建式類比數位轉換器之自我校正方法★ 多模組之相位同步技術
★ 使用低增益寬頻率調整範圍壓控震盪器 之1.25-GHz八相位鎖相迴路★ 高速傳輸連結網路的分析和模擬
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 在這篇論文中,我們提出了一個新的內建式自我測試的方法,可以用來測試在同一個晶片上之類比數位與數位類比轉換器之線性度。內建在同一個晶片上之數位訊號處理及微處理單元亦是可以用來計算測試結果的測試資源,因此我們提出的這個架構也可以充分的利用這些資源。為了不要因為外加的測試電路來降低整個系統的效能,我們的測試電路加越少越好。在處理測試的資料方面,超量取樣的統計方式在這裡可以有效的被運用。我們所提出的測試方法與機制亦是易於控制和分析的。
摘要(英) In this thesis, a new test methodology of BIST for on-chip ADC-DAC pair linearity testing is proposed. The on-chip digital signal processing unit and micro processing unit are used as test sources for calculating the test results. Hence, the on-chip test resources are fully used for our testing methodology. The test circuits are added as few as possible to prevent performance degradation of the overall system. To reduce the influence of system noise, the statistical methodology of oversampling is used. The proposed BIST scheme is ease of control and analysis.
關鍵字(中) ★ 內建式自我測式
★  數位類比轉換器
★  混合信號測試
★  非線性度
★  類比數位轉換器
關鍵字(英) ★ ADC
★  BIST
★  DAC
★  mixed-signal testing
★  nonlinearity
★  testing
論文目次 1. Introduction
1.1 Motivation
1.2 ADC/DAC Testing Methodologies Overview
1.3 Thesis Organization
2. Survey of ADC/DAC Testing Methodologies
2.1 Introduction
2.2 ADC Testing Methodologies
2.2.1 Static Test Method
2.2.2 Dynamic Test Method: Histogram Testing
2.2.3 Dynamic Test Method: FFT Testing
2.3 DAC Testing Methodologies
2.4 BIST for DAC-ADC Pair
3. Proposed Methodology for on-chip ADCs/DACs Testing
3.1 Introduction
3.2 BIST Structure for On-Chip ADCs/DACs Testing
3.3 Testing Strategy and Consideration
3.4 Simulation Results
3.4.1 Phase 1: Deriving the output codes of the
reference voltages
3.4.2 Phase 2: Time constant determination and ADC INL
3.4.3 Phase 3: Deriving integral nonlinearity of the DAC
4. Hareware Testing Results
4.1 Introduction
4.2 Test Environment
4.3 Test Results
4.3.1 Phase 1 test results
4.3.2 Phase 2 test results
4.3.3 Phase 3 test result
5. Conclusions
參考文獻 [1] J. Weimer, K. Baade. J. Fitzsimmons, B. Lowe, “A Rapid Dither Algorithm Advances A/D Converter Testing”, IEEE International Test Conference 1990, pp.498-507
[2] S. Max, “Fast, Accurate and Complete ADC Testing”, International Test Conference 1989, pp. 111-117.
[3] R. Martins, A. M., C. Serra, “Automated ADC Characterization Using the Histogram Test Stimulated by Gaussian Noise”, IEEE Transactions on Instrument and Measurement, VOL.48, NO.2, pp. 471-474.
[4] R. Martins, A. M. C. Serra , “The Use of a Noise Stimulus in ADC characterization”, Electronics, Circuits and Systems, 1998 IEEE International Conference on Volume: 3 , 1998 , Page(s): 457 -460 vol.3
[5] F. Azais, S. Bernard, Y. Bertrand, M. Renovell ,“Toward an ADC BIST Scheme Using the Histogram Test Technique”, European Test Workshop, 2000. Proceedings. IEEE , 2000 , Page(s): 53 —58.
[6] P. Carbone, D. Petri , “Noise Sensitivity of the ADC Histogram Test”, Instrumentation and Measurement, IEEE Transactions on Volume: 474 , Aug. 1998 , Page(s): 1001 —1004.
[7] IEEE Std 1057-1994, IEEE standard for digitizing waveform recorders, 30 Dec. 1994.
[8] Larrabee, J.H.; Hummels, D.M.; Irons, F.H.,” ADC compensation using a sinewave histogram method”, Instrumentation and Measurement Technology Conference,1997.IMTC/97.Proceedings,Sensing,Processing,Networking.,Vol.1,pp628-631,1997
[9] Ben-Hamida N., Ayari, B., Kaminska B., “Testing of Embedded A/D Converters in Mixed-Signal Circuit” , Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on , 1996 , Page(s): 135 —136.
[10] Zagursky, V.; Gertners, A., “Testing technique for embedded ADC”, Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on , 1998 , Page(s): 775 —778
[11] Mielke, J.A. ,“Frequency domain testing of ADCs”, IEEE Design & Test of Computers,Vol.13,pp64-69,1996
[12] Bellan D., Brandolini A., Gandelli A., “ADC nonlinearity and harmonic distortion in FFT Test”, Instrumentation and Measurement Technology Conference, 1998. IMTC/98. Conference Proceedings. IEEE Volume: 2 , 1998 , Page(s): 1233 -1238 vol.2
[13] Benetazzo L., Narduzzi C., Offelli C., Petri D., “A/D converter performance analysis by a frequency domain approach”, Instrumentation and Measurement Technology Conference, 1992. IMTC '92., 9th IEEE , 1992 , Page(s): 285 —289
[14] Hagelauer R., Oehler F., Rohmer G., Sauerer J., Seitzer D., Schmitt R., Winkler D., “Investigations and measurements of the dynamic performance of high-speed ADCs”, Instrumentation and Measurement, IEEE Transactions on Volume: 416 , Dec. 1992 , Page(s): 829 -833
[15] Arabi, K.; Kaminska, I.; Rzeszut, J., “BIST for D/A and A/D converters”, IEEE Design & Test of Computers, Volume: 13 Issue: 4 , Winter 1996 , Page(s): 40 —49
[16] Arabi, K.; Kaminska, I.; Rzeszut, J., “A built-in self-test approach for medium to high-resolution digital-to-analog converters”, Test Symposium, 1994., Proceedings of the Third Asian , 1994 , Page(s): 373 —378
[17] Hassan, I.H.S.; Arabi, K.; Kaminska, B., “Testing digital to analog converters based on oscillation-test strategy using sigma-delta modulation”, Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on, 1998 , Page(s): 40 -46
[18] Yun-Che Wen; Kuen-Jong Lee, “BIST structure for DAC testing”, Electronics Letters , Volume: 34 Issue: 12 , 11 June 1998 , Page(s): 1173 —1174
[19] Fasang, P.P., “An optimal method for testing digital to analog converters”, ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International , 1997
Page(s): 42 —46
[20] Fang Xu, “A new approach for the nonlinearity test of ADCs/DACs and its application for BIST”, Test Workshop 1999. Proceedings. European , 1999
Page(s): 34 —38
[21] Arabi, K.; Kaminska, I.; Rzeszut, J., “A New Built-in Self-test Approach For Digital-to-analog And Analog-to-digital Converters”, Computer-Aided Design, 1994., IEEE/ACM International Conference on Page(s): 491 -494
[22] Chin-Long Wey ,“Mixed-signal circuit testing-A review”, Proceedings of the Third IEEE International Conference,Vol.2,pp. 1064 —1067, 1996
[23] Mir, S.; Lubaszewski, M.; Liberali, V.; Courtois, B.,” Built-in self-test approaches for analogue and mixed-signal integrated circuits”, Circuits and Systems, 1995.,Proceedings.,Proceedings of the 38th Midwest Symposium, Vol.2, pp1145 —1150,1996
指導教授 蘇朝琴(Chauchin Su) 審核日期 2001-7-12
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明