以擴展基本角度CORDIC為基礎之低成本向量旋轉器矽智產設計

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：160

、訪客IP：3.144.36.141

姓名

何盈杰(Ying-Chieh Ho ) 查詢紙本館藏

畢業系所

電機工程研究所

論文名稱

以擴展基本角度CORDIC為基礎之低成本向量旋轉器矽智產設計
(COST-EFFICIENT DIGITAL IP DESIGN OF A HIGH-PERFORMANCE EEAS-CORDIC-BASED VECTOR ROTATOR)

相關論文

★ 即時的SIFT特徵點擷取之低記憶體硬體設計	★ 即時的人臉偵測與人臉辨識之門禁系統
★ 具即時自動跟隨功能之自走車	★ 應用於多導程心電訊號之無損壓縮演算法與實現
★ 離線自定義語音語者喚醒詞系統與嵌入式開發實現	★ 晶圓圖缺陷分類與嵌入式系統實現
★ 語音密集連接卷積網路應用於小尺寸關鍵詞偵測	★ G2LGAN: 對不平衡資料集進行資料擴增應用於晶圓圖缺陷分類
★ 補償無乘法數位濾波器有限精準度之演算法設計技巧	★ 可規劃式維特比解碼器之設計與實現
★ JPEG2000靜態影像編碼系統之分析與架構設計	★ 適用於通訊系統之低功率渦輪碼解碼器
★ 應用於多媒體通訊之平台式設計	★ 適用MPEG 編碼器之數位浮水印系統設計與實現
★ 適用於視訊錯誤隱藏之演算法開發及其資料重複使用考量	★ 一個低功率的MPEG Layer III 解碼器架構設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

向量旋轉（Vector Rotation）在數位信號處理中扮演著重要的角色，並且已經廣泛應用於許多數位信號處理的系統中，舉凡在非連續性正交轉換、數位晶格濾波器以及數位頻率合成器中，皆佔有舉足輕重的地位。然而，我們若直接用乘法器及加法器來實現向量旋轉則將耗費太多的硬體。於是，開發設計一個低成本且又高效率的向量旋轉器矽智產來取代是必要的。
數位座標旋轉器演算法(CORDIC Algorithm)是實現向量旋轉的一個好方法。在回顧一些CORDIC演算法之後，我們選擇了有具有低成本、高精確度及高速優點的擴展基本角度集合的CORDIC (EEAS-CORDIC)，並搭配前置旋轉的機制來達到更好的效能。
在現實的部分，我們針對關鍵的電路做深入的探討並在細節部分像是物理層級的改良以及係數方面的安排，都有仔細的考量。為了掌控我們的品質，我們採用全客戶流程設計來將我們的設計最佳化。在細部的設計中，我們使用的pass-nmos 邏輯的方式來實現滾桶式位移器以降低硬體上面積的耗費。模式選擇器的設計取代了原有的多工器來選擇不同的模式，這樣的設計不但可以比原來的設計減少大約13%的拉線面績，並且具備前置旋轉的功能。在加減法器部分我們則是利用了Carry Save Adder 與Carry Look-ahead Adder的技巧來提高我們EEAS- CORDIC IP的效能。另外，測試考量也包含在EEAS- CORDIC IP設計之中。我們採用台積電0.35um 1P4M CMOS的製程，而我們所設計出EEAS-CORDIC的矽智產核心面積只有0.133平方厘米並具有16位元的精確度。由後期模擬 (Post-simulation) 可知，EEAS-CORDIC矽智產可以操作在150MHz的工作頻率。相較於標準式元件設計，要比我們的設計多花上近6倍的硬體才能達到相同的速度要求。

摘要(英)

Vector rotation plays an important role in many Digital Signal Processing (DSP) systems, such as discrete orthogonal transform, lattice-based digital filter, and direct digital frequency synthesizer. However, it is not a cost-efficient way to realize the vector rotation directly with multipliers and adders. Instead, a well-designed, cost-efficient, and high-performance vector rotator IP is necessary.
COordinate Rotational DIgital Computer (CORDIC) algorithm is a well-known technique to perform the rotational operation in digital arithmetic. After reviewing some CORDIC algorithms, we choose Extended Elementary Angle Set (EEAS) due to its characteristic of low-complexity, high precision, and high speed. Besides, pre-rotation scheme can help us improve the performance of EEAS-CORDIC in advanced.
In the part of implementing the key components, we make a discussion for delicate design issues, such as physical improvements and parameters arrangements. In order to cost down the hardware complexity, we use pass-nmos logic technique to implement barrel shifters. We develop mode selectors to control the operation mode, and save about 13% area for wiring in original design. Besides mode selectors provide the function for pre-rotation scheme without any other redundant hardware cost. In part of adder/subtractor design, we use the technique of carry save adder and carry look-ahead adder to improve the performance of our EEAS-CORDIC IP. Testing issues, however, are also considered in our design. In order to guarantee the quality of our EEAS-CORDIC IP, we use full custom design flow to optimize our design. The IP is fabricated in tsmc 0.35um 1P4M CMOS process, and the core area of EEAS-CORDIC with 16-bit precision is only 0.133 mm*mm. The post-simulation shows the IP can be operated at 150MHz of clock rate using 3V supply voltage. Compared with standard cell design, standard cell spend about 6 times of cost under the similar timing condition.

關鍵字(中)

★ 前置旋轉
★ 向量旋轉器
★ 擴展基本角度集
★ 數位座標旋轉演算
★ 矽智產

關鍵字(英)

★ CORDIC
★ EEAS
★ pre-rotation
★ silicon intellectual property
★ vector rotator

論文目次

CHAPTER 1 INTRODUCTION1
1.1 BACKGROUND1
1.1.1 Fast Fourier Transform [21]1
1.1.2 Lattice-Based Digital Filter[4] [6]3
1.1.3 Direct Digital Frequency Synthesizer[6]3
1.2 MOTIVATION AND CONTRIBUTION5
1.3 THESIS ORGANIZATION6
CHAPTER 2 DESIGN ISSUES FOR DIGITAL HARD IP8
2.1 INTRODUCTION OF INTELLECTUAL PROPERTY8
2.1.1 Why Intellectual Property?8
2.1.2 Categorizations of IP9
2.2 SPECIFICATION REQUIREMENTS10
2.3 FULL CUSTOM DESIGN11
2.3.1 Functional Simulation12
2.3.2 Floor-planning12
2.3.3 Verification12
2.4 DESIGN FOR TESTABILITY[40]12
2.5 DOCUMENTATION[40]13
2.5.1 Contents of the user guide14
2.6 SUMMARY15
CHAPTER 3 REVIEW OF CORDIC-BASED ROTATORS16
3.1 CONVENTIONAL CORDIC[30]16
3.2 AR-CORDIC[33]17
3.3 EEAS-CORDIC[35]19
3.4 PRE-ROTATION SCHEME[34]22
3.5 SEARCHING ALGORITHMS23
3.5.1 Exhaustive Searching Algorithm[34]23
3.5.2 Greedy Algorithm[34]24
3.5.3 Trellis-based Searching Algorithm24
3.6 SUMMARY26
CHAPTER 4 IMPLEMENTATION OF EEAS-CORDIC IP27
4.1 MODIFIED VLSI ARCHITECTURE OF EEAS-CORDIC27
4.2 SPECIFICATION OF EEAS-CORDIC IP29
4.2.1 Determinate the Number of Stage of EEAS-CORDIC IP29
4.3 DESIGN FLOW AND ENVIRONMENTS29
4.4 IMPLEMENTATION OF KEY COMPONENTS31
4.4.1 Barrel Shifter31
4.4.2 Mode Selector33
4.4.3 Adder/Subtractor35
4.5 LAYOUT AND POST-SIMULATION OF EEAS-CORDIC IP40
4.6 DESIGN FOR TESTABILITY42
4.7 USER GUIDE OF EEAS-CORDIC DIGITAL IP42
4.8 SUMMARY46
CHAPTER 5 COMPARISONS OF ROTATIONAL CIRCUITS47
5.1 COMPARISONS WITH STANDARD CELL DESIGN47
5.2 COMPARISONS WITH MULTIPLIER-BASED ROTATOR49
5.3 SUMMARY50
CHAPTER 6 CONCLUSION AND FUTURE WORKS51
REFERENCES52

參考文獻

[1] A. M. Despain, “Fourier transform computers using CORDIC iterations, “ IEEE Trans. on Computers, vol. 23, pp. 993--1001, Oct. 1974.
[2] A. M. Despain, “Very fast Fourier transform algorithms for hardware implementation,” IEEE Trans. on Computers, vol. 28, pp.333--341, May 1979.
[3] P. P. Vaidyanathan, “A unified approach to orthogonal digital filters and wave digital filters based on the LBR two-pair extraction,” IEEE Trans. Circuits Syst., pp. 673-686, July 1985.
[4] A. Madisetti, A. Kwentus, and A. J. Willson, “A sine/cosine direct digital frequency synthesizer using an angle rotation algorithm,” in IEEE International Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, pp. 262-263, 1995.
[5] A. H. Gray, Jr. and J. D. Karkel, “Digital lattice and ladder filter synthesis,” IEEE trans. on Audio and Electroacoustics, vol. AU-21, pp.259-270, Dec 1973.
[6] Avanindra madisetti, Y. K. Alan, and Alan N. Willson Jr., ”A 100MHz, 16-b, direct digital frequency synthesizer with a 100-dbc spurious-free dynamic range,” IEEE Journal of Solid-State Circuits, vol. 34, no. 8, pp. 1034-1043, Aug. 1999.
[7] A. H. Gray, Jr. and J. D. Karkel, “A Normalized digital filter structure,” IEEE trans. on Acoustics, Speech, and Signal Processing, vol. ASSP-23, pp.268-277, June 1975.
[8] Y. H. Hu and Z. Wu, “An efficient CORDIC array structure for the implementation of discrete cosine transform,” IEEE Trans. on Signal Processing, vol. 43, pp. 331--336, Jan. 1995.
[9] A. Y. Wu, K. J. R. Liu, and A. Raghupathy, “System architecture of an adaptive reconfigurable DSP computing engine,” IEEE Trans. Circuits Syst. Video Technol., vol.8, pp. 54-73, Feb. 1998.
[10] J. H. Hsiao, L. G. Ghen, T. D. Chiueh, and C. T. Chen, “High throughput CORDIC-based systolic array design for the discrete cosine transform,” IEEE Trans. Circuits Syst. Video Technol., vol. 5, pp. 218--225, Jan. 1995.
[11] Ulrich Reimers, “Digital Video Broadcasting (DVB): The future of television,” in Physics World, April 1998.
[12] ETS 300 401, “Radio broadcasting system: Digital Audio Broadcasting (DAB) to Mobile, Portable and Fixed Receivers,” ETSI 2nd edition, May 1997.
[13] Y. Wu and W. Y. Zou, “Orthogonal frequency division multiplexing: A multi-carrier modulation scheme," IEEE Trans. Consumer Electronics, vol. 41, No. 3, Aug. 1995.
[14] John Stott (BBC), “DVB-T and the Magic of COFDM,” Web ssite at URL: http:// www.dvb.org/dvb_articles/dvb_articles.htm
[15] N. Weste and D. J. Skellern, “VLSI for OFDM,” IEEE Communications Magazine, Oct. 1998.
[16] Jacky S. Chow, Jerry C. Tu and John M. Cioffi, “A Discrete Multitone Transceiver System for HDSL Applications,” IEEE Journal on selected areas in Commun., vol. 9, No. 6, pp. 859-908, Aug. 1991.
[17] Lee, J. S. Chou, and J. M. Cioffi, “Performance evaluation of a fast computation algorithm for the DMT in high-speed subscriber loop,” IEEE J. Select. Areas Commun., vol. 13, pp. 1560-1570, Dec. 1995.
[18] Alan V. Oppenheim and Ronald W. Schafer “Discrete time signal processing, 2nd edition,” Prentice Hall.
[19] A. Y. Wu and T. S. Chan, “Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology,” IEEE Int. Conf. Acoust., Speech, and Signal Processing, vol. 6, pp. 3517-3520, Apr. 1998.
[20] K. J. Ray Liu, C. T. Chiu, R. K. Kolagotla, and J. F. J'aJ'a, “Optimal unified architectures for the real-time computation of time-recursive discrete sinusoidal transforms,” IEEE Trans. Circuits and Systems for Video Technology, vol. 4, no. 2, pp. 168-180, Apr. 1994.
[21] Bong-II Park, In-Cheol Park, and Chong-Min Kyung, “A regular layout structured multiplier based on weighted carry-save adder,” IEEE, pp. 243-248, 1999.
[22] G. B. Richard, Xingcha Fan, and Neil W. Bergmann, “An 180MHz 16 bit multiplier using asynchronous logic design techniques,” IEEE Custom Integrated Circuits Conference, pp 215-218, 1994
[23] Bryan W. Stiles and Earl E. Swartzlander Jr., “Pipelined parallel multiplier implementation,” IEEE, pp. 364-368, 1993.
[24] Shyh-Jye Jou, Chang-Yu Chen, En-Chung Yang, and Chau-Chin Su, ”A pipelined multiplier-accumulator using a high-speed low-power static and dynamic full adder design,” IEEE Journal of Solid-State Circuits, vol. 32, no. 1, pp. 114-118, Jan. 1997.
[25] Jinn-Shyan Wang and Po-Hui Yang, “Power analysis and implementation of a low-power 300MHz 8-b x 8-b pipelined multiplier,” IEEE, pp. 364-368, 2000.
[26] S. He and M. Torkelson. “A new approach to pipeline FFT processor,” IEEE Proceedings of IPPS'96.
[27] J. Hormigo, J. Villalba, and E. Zapata, “Interval sine and cosine functions computation based on variable-precision CORDIC algorithm,” in 14th IEEE Symposium on Computer Arithmetic, 1999. Proceedings., pp. 186-193, 1999.
[28] J. Vankka, M. Kosunen, J. Hubach, and K. Halonen, “A CORDIC-based multicarrier QAM modulator,” Global Telecommunications Conference, 1999, pp. 173 --177, 1999.
[29] K. Hwang, Computer Arithmetic: Principles, Architecture and Design. New York: Wiley, 1979.
[30] Y. H. Hu, “CORDIC-based VLSI architectures for digital signal processing,” IEEE Signal Processing Magazine, pp. 16-35, July 1992.[31] J. E. Volder, “The CORDIC trigonometric computing technique,” IRE Trans. on Electronic Computers, vol. 8, pp. 330-334, Sept. 1959.
[32] J. S. Walther, “A unified algorithm for elementary functions,” Spring Joint Computer Conf., pp. 379-385, 1971.
[33] Y. H. Hu and S. Naganathan, “An angle recoding method for CORDIC algorithm implementation,” IEEE Trans. on Computers, vol. 42, pp. 99-102, Jan. 1993.
[34] C. S. Wu and A. Y. Wu, “Modified vector rotational CORDIC (MVR-CORDIC) algorithm and its application to FFT,” in Proc. IEEE Int. Symp. Circuits and Systems, pp. 529-532, 2000.
[35] C. S. Wu and A. Y. Wu, “A novel rotational VLSI architecture based on extended elementary-angle set CORDIC algorithm,” in Proc. IEEE 2nd IEEE Asia Pacific Conference on ASICs, (Cheju, Korea), pp. 111-114, 2000.
[36] C. S. Wu and A. Y. Wu, “A new trellis-based searching scheme for EEAS-based CORDIC algorithm.” to appear in Proceeding of IEEE Int. Conf. Acoust. Speech, Signal Processing, Salt Lake City, 2001.
[37] A. Y. Wu and C. S. Wu, “A Unified Design Framework for Vector Rotational CORDIC Family Based on Angle Quantization Process,” to appear in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2001), Salt Lake City, May 2001.
[38] Jack E. Volder, “The CORDIC Trigonometric Computing Technique,” IRE Trans. on Electronic Computers, vol. 8, No. 3, pp.330-334, Sept., 1959.
[39] J. S. Walther, “A Unified Algorithm for Elementary Functions,” Spring Joint Computer Conf., pp.379-385, 1971.
[40] Michael Keating, Pierre Bricaud, “Reuse Methodology Manual for SoC designs”, 2nd edition, Kluwer Academic Publisher, 1999.

指導教授

蔡宗漢(Tsung-Han Tsai)

審核日期

2001-7-2

推文