內建式類比數位轉換器之自我校正方法

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陳鴻愷(Hung-Kai Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

內建式類比數位轉換器之自我校正方法
(A Self Calibrated ADC BIST Methodology)

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摘要(中)

本論文自我校正的方法是為了克服系統內建自我測試電路中，因製程飄移的誤差所提出解決的方法。利用在同一晶片上的數位訊號處理器或是微處理器，來進行測試結果的資料分析。所提出的方法只需藉由四個電阻與一個電容，純被動元件即可。這是非常容易控制與分析的。我們提出了兩種方法，一個是統計的方法，另一種為曲線比較的方式。利用離散元件來實際組裝硬體電路，模擬內建自我測試電路的類比數位轉換器。實驗結果驗證了此方法的可能性。所提出的兩種量測方法與IEEE1057測試方法的誤差均小於2LSB。

摘要(英)

A self calibrated BIST methodology is proposed to overcome the process variation of the BIST circuitry. The on-chip digital signal processor or micro processor can be used as data analyzer for test result analysis. The proposed methodology can be generated via passive components only, four resistors and one capacitor. It is very ease to control and analysis. Two test methods are proposed, one by statistical analysis and another by curve fitting. Test hardware is built by discrete components to emulate the ADC BIST circuitry. Experimental results verify the feasibility of the methodology. The differences between both methods with IEEE Std.1057 method are within 2LSB for a 12-bit ADC.

關鍵字(中)

★ 測試方法
★ 類比數位轉換器

關鍵字(英)

★ ADC
★ Testing

論文目次

1. Introduction 1
1.1 Motivation 1
1.2 ADC Testing Method Overview 2
1.3 Thesis Overview 3
2. Survey of ADC Test Methods 4
2.1 Ramp Waveform Test 4
2.2 Histogram Analysis 6
2.3 Curve Fitting Method 9
2.4 Frequency Domain Analysis 13
3. BIST Methodology 16
3.1 BIST Architecture 16
3.2 BIST Method 1: Statistical Analysis 18
3.2.1 Voltage Calibration 18
3.2.2 Time Constant Calibration 19
3.2.3 Gain and Offset Error Testing 19
3.2.4 Linearity Error Testing 20
3.3 BIST Method 2: Curve Fitting 21
3.4 Summary 22
4. Noise Reduction Technique and Analysis 24
4.1 Power of Averaging 24
4.2 Time Constant Error Budget 25
4.3 Voltage Calibration Error Budget 26
4.4 Over Sampling Ratio 27
5. Emulation and Measurement Results 29
5.1 Test Environment 29
5.2 Matlab Algorithm 31
5.3 Measurement Result 32
6. Conclusions 38

參考文獻

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指導教授

蘇朝琴(Chau-Chin Su)

審核日期

2002-7-9

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