博碩士論文 89521007 詳細資訊


姓名 麥世達(Shi-Dai Mai)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 多模組相位同步技術
(Multi-module synchronization methodology)
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摘要(中) 在此論文中,我們提出兩種多模組相位同步技術。第一種同步架構主要描述板子上的多模組相位同步問題。第二種同步架構主要描述單一晶片的多模組相位同步問題。這兩種同步技術目前是適合應用於整合自動測試機臺的多通道時序同步問題及大型SOC系統的環境。我們利用微調相位機制去減少模組間的時序誤差(timing skews)並提供一穩定的相位。兩種架構分藉由TSMC 0.35 µm 1P4M CMOS 和 TSMC 0.18 µm 1P6M的製程技術設計製作。電路最高工作頻率分別為200MHz 及1GHz。在架構一的量測結果,再初始時序誤差800ps及抖動( clock jitter)50ps的條件下,板子上的五個模組的相位誤差可拉近至100ps以內。在架構二的模擬結果,再初始時序誤差800ps及抖動( clock jitter)20ps的條件下,單一晶片內的五個模組的相位誤差可拉近至80ps以內。
摘要(英) In this thesis, we propose two novel multi-module synchronization mechanisms. The first architecture describes a board level multiple modules synchronization. The second architecture describes an on-chip multiple modules synchronization. The two techniques target the synchronization for test channels in automatic test equipment (ATE) and system on a chip (SOC) environment respectively. We utilize fine tune mechanisms to suppress timing skews between modules and provide the highly stable phase. Both multi-module synchronization are based on TSMC 0.35 µm 1P4M CMOS and TSMC 0.18 µm 1P6M CMOS processes respectively. The results are at 200MHz and 1GHz respectively. The measurement and simulation results show that on-board architecture is capable of reducing the skew of the five modules to less than 100ps and the clock frequency up to 200MHz with 50ps clock jitter when the initial skew of each module is as large as 800ps. The simulation results also show that on-chip architecture reduces the skew of the five modules to less than 80ps and the clock frequency up to 1GHz with 20ps clock jitter when the initial skew of each module is as large as 800ps
關鍵字(中) ★ 鎖相迴路
★ 自動測試機台
★ 同步
關鍵字(英) ★ PLL
★ ATE
★ synchronization
論文目次 CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 SURVEY OF THE TIMING GENERATION AND MEASUREMENT 2
1.3 A DYNAMIC CLOCK DISTRIBUTION TECHNIQUE 5
1.4 THESIS ORGANIZATION 6
CHAPTER 2 THE ARCHITECTURE OVERVIEW 8
2.1 OVERVIEW 8
2.2 MULTI-MODULE SYNCHRONIZATION MECHANISM 10
2.3 THE SYNCHRONOUS DIGITAL CONTROL LOGIC 12
2.3.1 PN FRAME DETECTION FSM CIRCUIT 14
2.3.2 DATA EXTRACTION CIRCUIT 14
2.3.3 LEAD/LAG PHASE DETECTION WITH PN SEQUENCE 15
2.3.4 PN GENERATION 16
2.3.5 PHASE ADJUSTMENT CIRCUIT 16
2.3.6 ADDRESS DECODER 17
2.4 THEORETICAL ANALYSIS OF THE PHASE DETECTION 18
CHAPTER 3 ON-CHIP MULTI-MODULE SYNCHRONIZATION 21
3.1 OVERVIEW 21
3.2 THE LINEAR MODEL OF THE PLL 23
3.3 THE CIRCUIT DESIGN OF THE PHASE LOCK LOOPS 25
3.3.1 PHASE FREQUENCY DETECTOR 25
3.3.2 CHARGE PUMP 27
3.3.3 LOOP FILTER 28
3.3.4 VOLTAGE CONTROLLED OSCILLATOR 29
3.3.5 FREQUENCY DIVIDER 32
3.4 NOISE ANALYSIS IN PLL CIRCUIT 33
3.5 MULTI-MODULE SYNCHRONIZATION MECHANISM 36
CHAPTER 4 SIMULATION AND MEASUREMENT RESULT 45
4.1 DESIGN FLOW OF MULTI-MODULES SYNCHRONIZATION 45
4.2 THE SIMULATION OF MULTI-MODULE SYNCHRONIZATION 47
4.3 THE IMPLEMENTATION OF MULTI-MODULES SYNCHRONIZATION 49
4.4 THE MEASUREMENT OF SYNCHRONIZATION MODULE 51
4.4.1 THE MEASUREMENT OF THE SINGLE MODULE 52
4.4.2 THE MEASUREMENT OF THE MULTI-MODULE SYSTEM 56
4.5 THE SIMULATION OF THE ON-CHIP MULTIPLE MODULES 59
CHAPTER 5 CONCLUSION 63
BIBLIOGRAPHY 64
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指導教授 蘇朝琴(Chau-Chin Su) 審核日期 2002-7-8

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