多模組相位同步技術

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：12

、訪客IP：3.144.244.44

姓名

麥世達(Shi-Dai Mai) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

多模組相位同步技術
(Multi-module synchronization methodology)

相關論文

★ 匯流排上的時間延遲及交談失真的偵錯設計技巧	★ 適用於自動測試機台的時間產生器
★ 混波測試匯流排的量測學	★ 高速連結之時序與資料回復
★ 基於IEEE 1057之類比數位轉換器量測技術	★ 應用於高畫質電視之載波回復電路架構
★ 單晶片測試機之前端驅動電路設計	★ 系統晶片類比數位轉換器測試之數位信號處理程式庫
★ A 2.5V,0.35um,2.5Gbps 傳送接收器設計	★ 內建式類比數位/數位類比轉換器線性度之自我測試
★ 高準確度及低成本之電壓量測技術	★ 應用於ATSC VSB時脈回復之全數位延遲線迴路
★ 適用於晶片間通訊之高速傳輸介面	★ 內建式類比數位轉換器之自我校正方法
★ 多模組之相位同步技術	★ 使用低增益寬頻率調整範圍壓控震盪器之1.25-GHz八相位鎖相迴路

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

在此論文中，我們提出兩種多模組相位同步技術。第一種同步架構主要描述板子上的多模組相位同步問題。第二種同步架構主要描述單一晶片的多模組相位同步問題。這兩種同步技術目前是適合應用於整合自動測試機臺的多通道時序同步問題及大型SOC系統的環境。我們利用微調相位機制去減少模組間的時序誤差(timing skews)並提供一穩定的相位。兩種架構分藉由TSMC 0.35 µm 1P4M CMOS 和 TSMC 0.18 µm 1P6M的製程技術設計製作。電路最高工作頻率分別為200MHz 及1GHz。在架構一的量測結果，再初始時序誤差800ps及抖動( clock jitter)50ps的條件下，板子上的五個模組的相位誤差可拉近至100ps以內。在架構二的模擬結果，再初始時序誤差800ps及抖動( clock jitter)20ps的條件下，單一晶片內的五個模組的相位誤差可拉近至80ps以內。

摘要(英)

In this thesis, we propose two novel multi-module synchronization mechanisms. The first architecture describes a board level multiple modules synchronization. The second architecture describes an on-chip multiple modules synchronization. The two techniques target the synchronization for test channels in automatic test equipment (ATE) and system on a chip (SOC) environment respectively. We utilize fine tune mechanisms to suppress timing skews between modules and provide the highly stable phase. Both multi-module synchronization are based on TSMC 0.35 µm 1P4M CMOS and TSMC 0.18 µm 1P6M CMOS processes respectively. The results are at 200MHz and 1GHz respectively. The measurement and simulation results show that on-board architecture is capable of reducing the skew of the five modules to less than 100ps and the clock frequency up to 200MHz with 50ps clock jitter when the initial skew of each module is as large as 800ps. The simulation results also show that on-chip architecture reduces the skew of the five modules to less than 80ps and the clock frequency up to 1GHz with 20ps clock jitter when the initial skew of each module is as large as 800ps

關鍵字(中)

★ 鎖相迴路
★ 自動測試機台
★ 同步

關鍵字(英)

★ PLL
★ ATE
★ synchronization

論文目次

CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 SURVEY OF THE TIMING GENERATION AND MEASUREMENT 2
1.3 A DYNAMIC CLOCK DISTRIBUTION TECHNIQUE 5
1.4 THESIS ORGANIZATION 6
CHAPTER 2 THE ARCHITECTURE OVERVIEW 8
2.1 OVERVIEW 8
2.2 MULTI-MODULE SYNCHRONIZATION MECHANISM 10
2.3 THE SYNCHRONOUS DIGITAL CONTROL LOGIC 12
2.3.1 PN FRAME DETECTION FSM CIRCUIT 14
2.3.2 DATA EXTRACTION CIRCUIT 14
2.3.3 LEAD/LAG PHASE DETECTION WITH PN SEQUENCE 15
2.3.4 PN GENERATION 16
2.3.5 PHASE ADJUSTMENT CIRCUIT 16
2.3.6 ADDRESS DECODER 17
2.4 THEORETICAL ANALYSIS OF THE PHASE DETECTION 18
CHAPTER 3 ON-CHIP MULTI-MODULE SYNCHRONIZATION 21
3.1 OVERVIEW 21
3.2 THE LINEAR MODEL OF THE PLL 23
3.3 THE CIRCUIT DESIGN OF THE PHASE LOCK LOOPS 25
3.3.1 PHASE FREQUENCY DETECTOR 25
3.3.2 CHARGE PUMP 27
3.3.3 LOOP FILTER 28
3.3.4 VOLTAGE CONTROLLED OSCILLATOR 29
3.3.5 FREQUENCY DIVIDER 32
3.4 NOISE ANALYSIS IN PLL CIRCUIT 33
3.5 MULTI-MODULE SYNCHRONIZATION MECHANISM 36
CHAPTER 4 SIMULATION AND MEASUREMENT RESULT 45
4.1 DESIGN FLOW OF MULTI-MODULES SYNCHRONIZATION 45
4.2 THE SIMULATION OF MULTI-MODULE SYNCHRONIZATION 47
4.3 THE IMPLEMENTATION OF MULTI-MODULES SYNCHRONIZATION 49
4.4 THE MEASUREMENT OF SYNCHRONIZATION MODULE 51
4.4.1 THE MEASUREMENT OF THE SINGLE MODULE 52
4.4.2 THE MEASUREMENT OF THE MULTI-MODULE SYSTEM 56
4.5 THE SIMULATION OF THE ON-CHIP MULTIPLE MODULES 59
CHAPTER 5 CONCLUSION 63
BIBLIOGRAPHY 64

參考文獻

[1] D. F. Wann and M. A. Fanklin, “Asynchronous and clocked control structures for VLSI based interconnections networks,” IEEE Trans. Computer., pp. 284-293, Mar. 1983.
[2] Ting-Hai Chao et al., “Zero skew clock net routing ,” 29th ACM/IEEE Design Automat. Conf. Digest Tech. Paper. pp. 518-523, 1992.
[3] F. Minami and M. Takano, “Clock tree synthesis based on RC delay balancing,” IEEE 1992 Custom Integrated Circuits Conf. Computer-Aided Digest of Tech. pp28.3.1-28.3.4, 1992.
[4] Ren-Song Tsay, “Exact zero skew,” in IEEE Intl. Conf. Comput.-Aided Design Digest Tech. Papers, pp. 336-339, 1991.
[5] S. Boon et. al., “High performance clock distribution for CMOS ASICs,” in IEEE 1989 Custom Integrated Circuits Conf. Computer-Aided Digest of Tech. pp15.4.1-15.4.5, 1989.
[6] F. Minami, and M. Takano, “Clock tree synthesis based on RC delay balancing” IEEE 1992 Custom Integrated Circuits Conference. Digest of Tech. Papers, 1992, pp: 28.3.1-28.3.4.
[7] Ramanathan, P., Dupont, A.J., Shin, K.G. “clock distribution in general VLSI circuits”, Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on , Volume: 41 Issue: 5 , May 1994, pp: 395 -404
[8] Joon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung, “A floorplan-based planning methodology for power and clock distribution in ASICs”, Design Automation Conference, 1999. Proceedings. 36th , 1999 pp: 766 -771
[9] Ren-Song Tsay, “Exact zero skew,” in IEEE Intl. Conf. Computer-Aided Design Digest Tech. Papers, 1991, pp: 336-339
[10] Hyun Lee, Han Quang Nguyen, Potter, D.W. ”Design self-synchronized clock distribution networks in an SoC ASIC using DLL with remote clock feedback” ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International , 2000
[11] Brueske, D.E., Embabi, S.H.K. “A dynamic clock synchronization technique for large systems” Components, Packaging, and Manufacturing Technology, Part B, Volume: 17 Issue: 3 , Aug. 1994 pp: 350 -361
[12] Mark Burns, Gordon W.Roberts. An Introduction to Mixed-Signal IC Test and Measurement, OXFORD university press, 2001
[13] Restle, P.J., Deutsch, A. “Design the best clock distribution network”, VLSI Circuits. Digest of Technical Papers. 1998 Symposium, 1998 pp(s): 2 -5
[14] S. Boon et. al, “High performance clock distribution for CMOS ASICs,” in IEEE 1989 Custom Integrated Circuits Conference. Digest Tech. Papers. pp: 15.4.1-15.4.5.
[15] Pangjun, J. Sapatnekar, S.S. “Clock distribution using multiple voltage,” Proc. Int’l Symp. Of Low Power Electronics and Design, 1999, pp. 145-150.
[16] Taylor, G.. F., Geannopoulos, G. “Microprocessor clock distribution,” IEEE 5th Technical Meeting on Electrical Performance of Electronic Packaging, 1996, pp29.
[17] S. F. Dow, J. M. Flasck and M. E. Levi, “A CMOS Delay Locked Loop and Sub-Nanosecond Time-to-Digital Convert Chip,” IEEE Transaction on Nuclear Science, vol. 43, Jam. 1996
[18] Roland E. Best, Phase-Locked Loops: Theory, Design, and Applications, McGraw-Hill Inc., 2nd ed., 1993
[19] Behzad Razavi, “Monolithic Phase-Locked Loops and Clock Recovery Circuits”, pp. 1-39, IEEE Press, 1996.
[20] I. A. Young. “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessor,” IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp 1599-1607, Nov. 1992.
[21] L. Kyoohyun, “A Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization,” IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp 807-815, June. 2000.
[22] V. V. Kaenel. “A 320MHz, 1.5mW @ 1.35V CMOS PLL for microprocessor Clock Generation ” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp 1715-1722, Nov. 1996.
[23] H. Notani, “A 622-MHz CMOS Phaes-Locked Loop with Precharge-type Phase Frequency Detector, ” in Symposium on VLSI Circuits, Dig. Tech. Papers, pp 129-130, June 1994
[24] M. Mizuno. “A 0.18um CMOS Hot-Standby Phase-Locked Loop Using a Noise-Immune Adaptive-Gain Voltage-Controlled Oscillator,” in ISSCC Dig. Tech. Papers, pp 268-269, Feb. 1995.
[25] John G. Maneatis. “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp 1723-1732, Nov. 1996.
[26] Won-Hyo Lee “A High Speed and Low Power Phase-Frequency Detector and Charge-pump” Proceedings of the ASP-DAC ’’99. Asia and South Pacific ,
vol. 1, pp 269 -272 1999.
[27] Lizhong Sun, “A 1.25-GHz 0.35um Monolithic CMOS PLL Based on Multiphase Ring Oscillator,” IEEE Journal of Solid-State Circuits, vol. 36, no. 6, pp 1723-1732, JUNE. 2001.
[28] K. B. Kim, D. Helman, and P. Gray, “A 30-MHz hybrid analog-digital clock recovery circuit in 2-um CMOS,” IEEE Journal of Solid-State Circuits, vol. 25, pp 1385-1394, Dec. 1990.
[29] S.K.Enam and A. Abidi, “NMOS ICs for clock and data regeneration in gigabit-per-second optical-fiber receivers,” IEEE Journal of Solid-State Circuits, vol. 27, pp 1763-1774, Dec. 1992.
[30] Koichiro Minami “A 0.10um CMOS, 1.2V, 2GHz Phase-Locked Loop with Gain Compensation VCO” IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE, pp 213-216, 2001
[31] J. Yuan and C. Svensson, “high speed CMOS circuit technique,” IEEE Journal of Solid-State Circuits, vol. 24, pp 62-70, 1989
[32] William B. Wilson, Un-Ku Moon, Kadaba R.Lakshmikumar, Liang Dai. “A CMOS Self-Calibrating Frequency Synthesizer,” IEEE Journal of Solid-State Circuits, 2000

指導教授

蘇朝琴(Chau-Chin Su)

審核日期

2002-7-8

推文