適用於通訊系統之低功率渦輪碼解碼器

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姓名

薛乃軒(Nai-Hsuan Hsueh) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用於通訊系統之低功率渦輪碼解碼器
(Low power Turbo decoder for communication system)

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摘要(中)

渦輪碼（Turbo Code）是在1993年由Berrou等人所提出，它是由兩個迴旋碼（Convolutional Code）平行鏈結編碼（parallel concatenation）而成，隨後是以反覆解碼（iteration decoding）的架構進行解碼，而在此反覆解碼的架構下，每個基本的解碼器都必須具有軟式輸入以及軟式輸出（SISO，Soft-input Soft-output）的能力。渦輪碼的錯誤更正能力很接近理論上的雪農極限（Shannon-limit），它強大的錯誤更正能力非常適合如第三代行動通訊（3GPP、3GPP2）等無線通訊傳輸系統的應用，以克服雜訊日益增強的通道。
在本論文中，我們實現了適用於WCDMA與CDMA2000系統之渦輪碼解碼器。相較於傳統的迴旋碼解碼器，渦輪碼解碼器的操作原理複雜了許多，且在實際硬體實現時，有許多要素需要列入考慮。目前在研究領域中，有數種演算法可以滿足此類具有軟式輸入及軟式輸出的架構，我們選擇了其中硬體複雜度較低、由Hagenauer所提出的軟式輸出維特比演算法（Soft-Output Viterbi Algorithm，SOVA）來實現我們的解碼器電路。在設計的過程中，我們針對實現軟式輸出維特比解碼器（SOVA Decoder）的要素加以探討，並且選定我們所要採用的架構；隨後，我們以Matlab程式驗證整個編解碼運作的過程，並以Verilog硬體描述語言來模擬及驗證電路的正確性。最後，我們將此電路轉換成電路設計並對應至CIC所提供的TSMC 0.35μm standard cell佈局成晶片。

摘要(英)

Turbo codes, proposed by Berrou et al. in 1993, which are parallel concatenated convolution codes joined through interleavers. Iterative decoding techniques are used for decoding. It has been shown that any decoder that accepts soft inputs (include a priori values) and generates soft outputs can be used for iterative decoding. Turbo code can achieve almost near Shannon limit error correction performance, its powerful error correcting capability is very attractive for mobile wireless applications to combat channel fading. Turbo code has been adopted as the channel coding schemes for the services of high transmission rates in a number of the 3rd generation mobile systems (3GPP), such as WCDMA and CDMA2000.
In this thesis, we focus on the realization of the soft-input and soft-output comment decoder. The operating algorithm of Turbo code decoder is much complicated than the conventional convolutional decoder, and there are several implementation issues. There are several algorithms that meet the requirements of the soft-input and soft-output structure. A Soft-Output Viterbi Algorithm (SOVA) proposed by Hagenauer is used to implement the soft-input and soft-output convolutional decoder. In realization, we first discuss the proposed architecture and the implementation issues. Then, the encoding/decoding process is simulated by Matlab program and verified by Verilog HDL. Finally, the architecture of the SOVA decoder is then mapped on circuit design, and the layout implementation is made by using TSMC standard cell and 0.35μm TSMC CMOS SPDM technology.

關鍵字(中)

★ 渦輪碼

關鍵字(英)

★ Turbo code
★ VLSI
★ SOVA

論文目次

Chapter 1 Introduction 14
1.1 Introduction to Turbo Code System 14
1.2 Motivation and Objective 15
1.3 Thesis Organization 17
Chapter 2 Turbo Code and the SOVA Algorithm 18
2.1 Encoding of Turbo Code 19
2.1.1 Parallel Concatenation of Convolutional Code 19
2.1.2 Interleaver 20
2.2 Decoding of Turbo Code 24
2.2.1 The Soft-Output Viertbi Algorithm (SOVA) 27
2.2.2 A simple example for SOVA-based Turbo code decoder 29
Chapter 3 Implementation Issues of Turbo decoder 43
3.1 CONVENTIONAL SOVA DECODER 43
3.1.1 One-Step SOVA Decoder (OS-SOVA) 43
3.1.2 Two-Step SOVA Decoder (TS-SOVA) 46
3.2 Modified Two-Step SOVA Decoder (MTS-SOVA) 47
3.3 Implementation Issues of Turbo Code Decoder 48
3.3.1 BMU Implementation Issues 49
3.3.2 ACSU Implementation Issues 51
3.3.3 SMU Implementation Issues 52
3.3.4 PCU and UU Implementation Issues 54
Chapter 4 Implementation of Turbo Decoder 57
4.1 IC Design Flow 57
4.2 Implementation Result 58
4.2.1 Design Specification 58
4.2.2 Matlab Simulation Results 59
4.2.3 Verilog Simulation Results 59
4.2.4 Chip layout and implementation results 60
Chapter 5 Conclusion 62
5.1 Summary 62
5.2 Future Work 62
Reference 64

參考文獻

[1] 3GPP TSG-RAN Working Group 1 (2001, Sept.) Physical channels and mapping of transport channels (FDD) (Release 4), TS25.211 v4.2.0.
[2] TIA/EIA/CDMA2000, Physical Layer Standard for CDMA2000 Standards for Spread Spectrum Systems, June ,2000
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[4] C. Berrou and A. Glavieux, “Near optimum error correcting coding and decoding. Turbo-codes,” IEEE Trans. Commun., vol. 44, no. 10, pp. 1261–1271, 1996.
[5] C. Berrou, P. Adde, E. Angui, and S. Faudeil, “A low complexity soft-output Viterbi decoder architecture,” in Proc. Int. Conf. Communica-tions, May 1993, pp. 737–740.
[6] Woodard, J.P.; Hanzo, L. Vehicular Technology “Comparative study of turbo decoding techniques: an overview ”, IEEE Transactions on , Volume: 49 Issue: 6 , Nov. 2000 Page(s): 2208 –2233
[7] J. Hagenauer, P. Hoeher, “A Viterbi Algorithm with soft-decision outputs and its applications,” Proceedings of IEEE 1989 Globecom Conference, p. 1680-1686.
[8] UWB paper
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[10] S. Lin and D. J. Costello, Jr., Error Control Coding, Prentice-Hall, New Jersey, 1982
[11] Feng Lo, FPGA Realization of the Viterbi Decoder for HDSL2 Systems, NCU thesis, June, 2000.
[12] C. Berrou, P. Adde, E. Angui, and S. Faudeil, “A low complexity soft-output Viterbi decoder architecture,” in Proc. Int. Conf. Communications, pp. 737–740 May 1993
[13] O. Joeressen, M. Vaupel, and H. Meyr, “High-speed VLSI architecture for soft-output Viterbi decoding” in Int. Conference on Application Specific Array Processors, pp.373-384, 1992
[14] S. Benedetto,a D. Divsalar,b G. Montorsi,a and F. Pollara, “Soft-Output Decoding Algorithms in Iterative Decoding of Turbo Codes” in TDA Progress Report 42-124, pp63-87, Feb. 1996
[15] Ivan M. Onyszchuk, “Truncation Length for Viterbi Decoding,” IEEE trans. on Commu., vol. COM-39, pp. 1023-1026, July 1991.
[16] P. J. Black and T. H. Y. Meng, “Hybrid Survivor Path Architecture for Viterbi Decoders,” in Proc. ICASSP 93, 1993, pp. I-433-I-436.
[17] J. Sparso, H. J. Jorgensen, E. Paaske, S. Pedersen and T. R. Petersen, “ An Area-Efficient Topology for VLSI Implementation of Viterbi Decoders and Other Shuffle-Exchange Type structures,” IEEE Journal of Solid-State Circuits, vol. 26, no. 2, Feb. 1991.
[18] Feng Lo, FPGA Realization of the Viterbi Decoder for HDSL2 Systems, NCU thesis, June, 2000.

指導教授

蔡宗漢(Tsung-Han Tsai)

審核日期

2002-7-17

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