適用在通訊應用之可參數化內嵌式數位信號處理器核心

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姓名

譚明烜(Ming-Hsuan Tan) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用在通訊應用之可參數化內嵌式數位信號處理器核心
(Parameterized and Embedded DSP Corefor Communication Applications)

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摘要(中)

在本篇論文中，實現了一顆可參數化的數位信號處理器。它是專用於通訊系統應用。除了提供一般十六位元數位處理器所具備的基本指令集外，還為了特別的功能硬體設計，提供特殊指令。這使得這顆數位信號處理器更適於計算密集的應用。
我們所提出的數位信號處理器具有幾項優越的特性：可參數化的架構，高速的效能，和低功率。我們設計了各種模組產生器以產生可變動(configurable)的資料路徑(datapath)和可重複使用的特殊功能硬體，並設計了一個模組產生器用以整合各個功能模組及產生數位信號處理器的硬體描述語言。平行化的架構也加速了效能，在效能測試程式中兩組乘法器串聯加法器減少一半的指令週期。為了減少功率耗損，我們採用許多種低功率設計技巧，如灰碼記憶體定址法和管線分享技巧等。
以模組產生器所產生的十六位元數位信號處理器為例，其最大工作效能可操作在140百萬指令。

摘要(英)

This thesis introduces the design and implementation of an embedded and parameterized digital signal processing (DSP) processor. Besides providing a basic instruction set that is similar to general DSP processors, it also contains unique instructions and optional special function blocks that make this DSP processor more efficient for computation-intensive applications.
The proposed DSP processor has some advanced features: a parameterized architecture, special functions for communication application, some low power designs and I/O for embedded consideration. By using window GUI and a Verilog code generator, dedicated DSP for specified application can be generated. In addition, we use high degree of parallelism to speed up its performance. The data path contains two Multiply-Accumulate units to reduce half instruction cycles in the operation of FIR filter. For consideration of reducing power consumption, we adopt some low power design such as gray code memory addressing and pipeline sharing techniques.
The chip will be implemented in a cell-based design method with a 0.25 1P5M cell library. The maximum operating frequency of a 16?16 DSP is 140MHz.

關鍵字(中)

★ 數位信號處理器
★ 可參數化
★ 內嵌式

關鍵字(英)

★ DSP
★ embedded
★ paraneterized

論文目次

CHAPTER 1 INTRODUCTION - 1 -
1.1. MOTIVATION - 1 -
1.2. APPLICATION-SPECIFIC DSP FOR COMMUNICATION AND EMBEDDED SYSTEM - 3 -
1.3. PARAMETERIZED DSP CORE - 4 -
1.4. THESIS ORGANIZATION - 6 -
CHAPTER 2 THE ARCHITECTURE OF DSP CORE - 7 -
2.1. THE OVERVIEW OF NCU_DSP_2002 ARCHITECTURE - 7 -
2.2. PROGRAM ADDRESS GENERATION UNIT (PAGU) - 8 -
2.2.1. Hardware Looping - 8 -
2.2.2. Conditional / Unconditional Branches, Calls and Returns - 12 -
2.3. DATA ADDRESS GENERATION UNIT (DAGU) - 13 -
2.4. MEMORY ARCHITECTURE - 17 -
2.5. COMPUTATION UNIT - 17 -
2.5.1. Data Path - 17 -
2.5.2. Application-Specific Function Block - 18 -
2.6. I/O BLOCK - 19 -
2.7. INSTRUCTION SET - 20 -
2.7.1. Arithmetic and Logic Operation - 21 -
2.7.2. Shift and Comparison Operation - 21 -
2.7.3. Program Flow Control - 22 -
2.7.4. Special Function Instructions - 22 -
CHAPTER 3 PARAMETERIZED DESIGN FLOW AND IMPLEMENTATION - 23 -
3.1. INTRODUCTION - 23 -
3.2. PARAMETERIZED AND CONFIGURABLE ARCHITECTURE - 23 -
3.3. PROGRAM ADDRESS GENERATION UNIT (PAGU) - 26 -
3.4. DATA ADDRESS GENERATION UNIT (DAGU) - 27 -
3.5. MEMORY ARCHITECTURE - 29 -
3.6. DATAPATH - 29 -
3.7. I/O BLOCK - 30 -
CHAPTER 4 LOW POWER DESIGNS - 32 -
4.1. LOW POWER ARCHITECTURE - 32 -
4.2. GRAY CODED ADDRESSING - 33 -
4.3. HARDWARE LOOPING - 35 -
4.4. PIPELINE SHARING - 38 -
CHAPTER 5 CHIP IMPLEMENTATION - 40 -
5.1. DESIGN FLOW - 40 -
5.2. SYNTHESIS RESULTS - 43 -
5.2.1. Design example - 43 -
5.2.2. First Version of our DSP Core — NCU_DSP - 45 -
5.3. TEST CONSIDERATION - 46 -
5.4. BENCHMARK SIMULATION - 47 -
CHAPTER 6 CONCLUSIONS AND FUTURE WORK - 49 -
APPENDIX: INSTRUCTION SET - 50 -
REFERENCE - 94 -

參考文獻

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指導教授

周世傑(Shyh-Jye Jou)

審核日期

2002-7-10

推文