5Gbps預先增強器之串列連結傳收機

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姓名

王長弘(Chun-Hong Wang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

5Gbps預先增強器之串列連結傳收機
(5Gbps serial link transceiver with pre-emphasis)

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摘要(中)

近年來，由於多媒體的應用，傳輸資料頻寬的需要量愈來愈大。高速串列連結己經達到每秒兆位元的速度，因為價格低廉，所以廣為應用。
本論文中，我們將完成高速串列連結之資料傳收機並且建構信號預先增強器電路於其中。首先，針對高速傳收機做一個概略的介紹和導讀。接下來，對纜線隨著長度和頻率而衰減的特性做詳細的說明。我們提出一個可以加大信號高頻區段的預先增強器電路，使得資料接收端全部的頻率響應在我們要傳的頻率區段內是一個定值。預先增強器電路可以處理長度為一公尺至十五公尺的纜線。整個電路將以TSMC 0.18um 1P6M的數位製程予以實現。這個傳收機在經過十公尺的纜線傳輸情況下仍可以達到傳輸速率5Gbps.

摘要(英)

Recently, due to the multimedia applications, the data transmission bandwidth requirement is increased. High-speed serial link that achieves Gbps has the advantage of low cost and thus become popular.
In this thesis, we will implement the high-speed data serial link transceiver and demonstrate the pre-emphasis circuit. The overviews of the high-speed transceiver will be introduced first. Then the cable attenuation with the length and frequency will be shown. We propose a pre-emphasis architecture that can enlarge the high frequency components, so the overall frequency response in receiver is uniform within our desired frequency range. The pre-emphasis circuit can handle cable length from 1m to 15m. The overall circuit is implemented in TSMC 0.18um 1P6M process. The performance of the transceiver can reach 5Gbps over the 10-meter long cable.

關鍵字(中)

★ 預先增強器

關鍵字(英)

★ cable
★ pre-emphasis

論文目次

Chapter 1 Introduction 1
1.1 Introduction of High-Speed Serial Link 1
1.2 Motivation and Goals 2
1.3 Thesis Organization 3
Chapter 2 Overview of High-Speed Link Transceiver 4
2.1 Introduction of Signaling Scheme 4
2.1.1 Incident and Reflection 5
2.2 Limitation of Signaling 7
2.2.1 Package Effect 8
2.2.2 Transmission Medium 10
2.3 Coaxial cable characteristics 13
2.4 Transmitter Pre-emphasis and Receiver Equalizer 16
2.5 Parallel Data Path Transceiver 18
2.6 Summary 19
Chapter 3 Architecture of The Transceiver 21
3.1 Introduction 21
3.2 Functional Blocks of Transmitter 23
3.2.1 PRBS 23
3.2.2 Synchronizer 24
3.2.3 Pre-Emphasis Tuning Scheme 24
3.2.4 Pre-Emphasis and Driver 26
3.2.5 Pre-emphasis and Driver 26
3.2.6 Adaptive Current Source 29
3.3 Receiver Design 30
3.3.1 Differential to Single Receiver 31
3.3.2 Adaptive pre-emphasis scheme 32
3.4 Summary 36
Chapter 4 Transceiver Circuit Design 37
4.1 Introduction 37
4.2 Transceiver Design Problem 38
4.3 Circuit Design and Simulation Results 38
4.3.1 Input Data 39
4.3.2 Synchronizer 39
4.3.3 2 Tap Pre-emphasis 41
4.3.4 Multiplexing Driver 42
4.3.5 On Chip Resistance 45
4.3.6 Receiver 45
4.3.7 PLL 46
4.4 Simulation Result 46
4.5 Implementations 48
4.6 Measurement and Testing Consideration 50
4.7 Comparison with Others 52
4.8 Summary 53
Chapter 5 Conclusions 54
Bibliography 55

參考文獻

[1] F.R. Ramin, “A CMOS 4-PAM Multi-Gbps Serial Link,” the degree of doctor of philosophy of Stanford University, August 2000.
[2] C.K. Ken Yang, “Design of High-speed Serial Links CMOS,” the degree of doctor of philosophy of Stanford University, December 1998.
[3] H. W. Johnson, G. Martin, High-Speed digital design. Prentice-Hall Inc, 1993.
[4] Avant! Star-Hspice Manual: Release 1999.4, December 1999.
[5] B.K. Sen, R.L. Wheeler, “Skin effects models for transmission line structures using generic spice circuit simulators,” IEEE, 1998.
[6] W.J. Dally, J. Poulto, “Transmitter equalization for 4-Gbps signaling,” IEEE Micro, 1997.
[7] M. Horowitz, C.K. Ken yang, “High-speed electrical signaling: overviews and limitations,” IEEE Micro, 1998
[8] C.K. Ken Yang and M.A. Horowitz, “A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links,” IEEE J. Solid-State Circuits, vol.31, No.12, pp.2015 –2023, Dec. 1996.
[9] C.K. Ken Yang, F.R. Ramin and M.A. Horowitz, “A 0.5-/spl mu/m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling Solid-State Circuits,” IEEE J. Solid-State Circuits, vol.33, No.5, pp.713 –722, May. 1998.
[10] K. Lee, S. Kim, G. Ahn and D.K. Jeong, “A CMOS serial link for fully duplexed data communication,” IEEE J. Solid-State Circuits, vol.30, No.4, pp.353 –364, April. 1995.
[11] Universal Serial Bus specification revision 2.0, Mar. 2000.
[12] IEEE Std 1394b-2000: IEEE standard for a high perf.
[13] RAMBus specification Version 1.11, July. 2000.
[14] IEEE Std 803.2: IEEE standard for 1000Mbps Ethernet.
[15] Http://www.jye.com.tw
[16] Http://www.belden.com

指導教授

周世傑(Shyh-Jye Jou)

審核日期

2002-7-12

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