博碩士論文 89521014 詳細資訊




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姓名 陳彥宏(Yen-Hung Chen)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 超取樣技術之資料回復電路設計及其模組產生器
(Module Generator of Data Recovery Circuits Using Oversampling Technique)
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摘要(中) 在此篇論文裡,我們介紹了使用超取樣方法的全數位式資料回復技術及電路架構應用在高速序列傳輸。一些重要效能和設計參數都會被分析及公式化以便不同的設計參數可以設計符合不同的規格。整個電路的架構非常規律和適合以標準庫存元件(standard-cell)的流程完成,因此使它非常適合當做軟矽智產(Soft Silicon Intellectual Property)。我們更進一步的建立一個模組產生器,它可以自動產生verilog語言。它亦可自動產生設計參數去處理超取樣架構以符合不同的規格。最後一個利用模組產生器的設計範例,將以TSMC 0.35um 1P4M的數位製程予以實現。此設計的最快工作效率可以達到1.9Gbps,且在3.3V的電壓下功率消耗為112.2mW。若無preamble的電路其效率可達2.09Gbps。
摘要(英) In this thesis, we introduce the technique and circuit architecture for the all-digital data recovery of high-speed serial link using an oversampling method. Several key performance and design parameters indices are analyzed and formulated so that different specification can be designed with different design parameters. The overall architecture is very regular and hence very suitable for standard cell implementation flow that makes it very suitable as a Soft Silicon Intellectual Property. Furthermore, we establish a module generator which can generate the design in verilog code automatically. It can automatically generate the design parameters to deal with the oversampling architecture to meet different specifications. Finally, a design example generated by the module generator is implemented in a cell-based design method using the TSMC 0.35 1P4M cell library. The maximum performance of the design can reach 1.9 Gbps with power consumption of 112.2mW at 3.3V. Without preamble circuit, the performance can reach 2.09 Gbps.
關鍵字(中) ★ 超取樣技術 關鍵字(英) ★ oversampling
論文目次 Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Motivation 3
1.3 Thesis Organization 5
Chapter 2 Overview of Data/Clock Recovery 6
2.1 Introduction 6
2.2 Transceiver Architecture and Data/Clock Recovery 6
2.3 Timing Margin and Jitter Analysis 15
2.4 Summary 17
Chapter 3 Oversampling Architecture and Theoretical Analysis 18
3.1 Introduction 18
3.2 Oversampling Architecture 19
3.3 Oversampling Design Problem 22
3.3.1 Initial Synchronization 22
3.3.2 Frequency Offset 23
3.4 Bit Error Rate Analysis 24
3.4.1 Analog Sampling 25
3.4.2 Digital Sampling 28
3.5 The Maximum Phase-tracking Rate 31
3.6 Summary 32
Chapter 4 The Oversampling Circuit Design 33
4.1 Introduction 33
4.2 Circuit Design 34
4.2.1 Multi-Phase DLL/PLL 35
4.2.2 Sampling Block and Transition Detector 35
4.2.3 Sliding Windows and Optimal Phase Decision 36
4.2.4 Byte synchronization and Elastic Buffer 38
4.2.5 Preamble 43
4.2.6 Timing of Overall Design 44
4.3 Simulation Result 45
4.4 Summary 46
Chapter 5 The Module Generator and Implementation 47
5.1 Introduction 47
5.2 Module Generator Design Flow 48
5.3 Design Example 50
5.4 Comparison 53
5.5 Measurement and Testing Consideration 54
5.6 Summary 54
Chapter 6 Conclusions 55
Bibliography 57
參考文獻 [1] Universal Serial Bus specification revision 2.0, Mar. 2000.
[2] RAMBus specification Version 1.11, July. 2000.
[3] IEEE Std 803.2: IEEE standard for 1000Mbps Ethernet.
[4] P1394b Draft Standard for a High Performance Serial Bus(Supplement), P1394b Draft 1.3.1, Oct 15, 2001.
[5] M.A. Horowitz, C.K. Ken Yang and Stefanos Sidiropoulos, “High-Speed Electrical Signaling: Overview and Limitations,” IEEE Micro, vol18, pp.12-24, Jan. 1998.
[6] F. R. Ramin, C.K. Ken Yang, M.A. Horowitz, Thomas H. Lee, “A 0.4-/spl mu/m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter,” IEEE J. Solid-State Circuits, vol.34, No.5, pp.580-585, May. 1999.
[7] H. Watanabe, K. Mori, S. Komatsubara, N. Fujimoto and T. Horimatsu, “Gb/s array LSIs for parallel optical links,” Gallium Arsenide Integrated Circuit Symposium, pp.291-294, Oct. 1993.
[8] R. S. Co, and J. H. Mulligan, Jr., “Optimization of phase-locked loop performance in data recovery systems,” IEEE J. Solid-State Circuits, vol.29, No.9, pp.1022-1034, Sept. 1994.
[9] C.K. Ken Yang and M.A. Horowitz, “A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links,” IEEE J. Solid-State Circuits, vol.31, No.12, pp.2015 –2023, Dec. 1996.
[10] IEEE std 1596.3_1996: IEEE Standard for Low-Voltage Differential Signals(LVDS) for scalable Coherent Interface(SCI), Mar. 1996.
[11] N. Kushiyama, et al. “A 500-Megabyte/s Data-Rate 4.5M DRAM”, IEEE Journal of Solid-State Circuits, vol. 28, No. 4, pp. 490-498, April 1993.
[12] S. Sidiropoulos, et. al, “A CMOS 500Mbps/pin Synchronous Point to Point LinkInterface,” Proceedings of 1994 IEEE Symposium on VLSI Circuits. Digest of Technical Papers, pp. 43-44, Jun. 1994.
[13] K. Y. Chang, “Design of A CMOS Asymmetric Serial Link,” PH.D dissertation, Dep. Elec. Eng., Stanford University, August 1999.
[14] K. Lee, S. Kim, G. Ahn and D. K. Jeong, “A CMOS Serial Link for Fully Duplexed data communication,” IEEE J. Solid-State Circuits, vol.30, No.4, pp.353 –364, April. 1995.
[15] Jitter Specification Made Easy: A Heuristic Discussion of Fibre Channel and Gigabit Ethernet Methods, Rev 0, Feb 6,2001.
[16] C. C. Kuo, “Data Recovery Using Oversampling Technique and Its Application in USB2,” M.S. dissertation, Dep. Elec. Eng., National Central University, Taiwan, May 2000.
[17] Fiber Channel-Methodologies for jitter Specification, T11.2/Project 1230/Rev 10, June. 1999.
指導教授 周世傑(Shyh-Jye Jou) 審核日期 2002-7-12
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