一個1.8V，10GHz CMOS之頻率合成器

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郭建良(Chien-Liang Kuo) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

一個1.8V，10GHz CMOS之頻率合成器
(A 1.8V，10GHz CMOS Frequency Synthesizer)

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摘要(中)

本論文目標在於使用台灣積體電路公司之0.18mm金屬氧化物半導體製程來實現一可應用於無線通訊領域及光通訊資料傳輸之頻率合成器，其中包含了多相位單晶壓控震盪器，可操作在10GHz之除頻電路,相位頻率偵測器，迴路濾波器及電荷充放電路。此論文可分為五個章節,第一章為對此頻率產生器之功能及應用上作一概略性的介紹。
第二章介紹以鎖相迴路來實現頻率合成器之原理及設計上的重點。並分析鎖相迴路，以冀能提升本頻率合成器之效能。由於本頻率合成器可分成幾個重要的區塊。1、相位/頻率偵測器(phase/frequency detector) 2、電荷充放器(charge pump) 3、迴路濾波器(loop filter) 4、壓控震盪器(voltage control oscillator) 5、除頻器(divider)。藉由這些區塊頻率合成器將成為一完整的回授迴圈。其中、將介紹其中之相位/頻率偵測器，電荷充放器和迴路濾波器之設計，並實現出一可達高解析度之相位/頻率偵測器，及全差動式之電荷充放電路。
第三章為介紹壓控震盪器之震盪原理及設計考量，並說明使用電感電容震盪器之原由，接下來，便以雙迴路電感電容震盪器方式來實現4相位輸出之電壓控制震盪器，並應用其理論使用電流模式改變輸出頻率，在此我們使用全差動式控制訊號來控制輸出之震盪頻率，並使用切換式可變電容來增加壓控震盪器之輸出頻率範圍，在這個章節的內容中，引入了Leeson's formula來對震盪器的雜訊做分析及整理。
第四章將介紹在回授路徑上之多除數除頻器,首先介紹了目前常用之多除數除頻器之架構,並提出改良之架構,以期達到可以對高頻信號除頻的目的,其中,本設計採用了注入鎖定式除頻器之原理，來設計前置除頻器，在本章中將敘述其理論依據及工作原理,並由此使用台灣積體電路公司之0.25mm金屬氧化物半導體製程驗證了除三及除五之注入鎖定式除頻器的設計，經量測後驗證之可除頻率分別為7.1GHz及18.1GHz,輸出信號之相位雜訊分別為-100 dBc/Hz @ 100K offset 及-101 dBc/Hz @ 100K offset。而在本頻率合成器的設計中，採用除八之注入鎖定式除頻電路，其輸出為8個相位均勻之信號，而利用此8個相位可以設計出可變動除數之前置除頻器，配合後方之屏蔽計數器(swallow counter)及可程式計數器(programmable counter)使用，最終可以設計出除數為512-518之除頻電路.
第五章為結論,將本論文之內容及目前之模擬,實作及量測作一總結.

摘要(英)

The fully integrated frequency synthesizer fabricated in TSMC 0.18um CMOS technology is presented. It is capable of using in SONET (Synchronous Optical Network) OC (Optical Carrier)-192 transceiver system and also RF receiver. This frequency synthesizer adopted a monolithic VCO (Voltage Control Oscillator) with quadrature phase outputs, which oscillates around 10GHz. In its feedback path the divider is used for multiply the input reference clock. This design the multi-modulus divider can change its divisor from 512 to 519. (or just 16 for OC-192) which capable of operating around 10GHz. For such operating frequency, the ILFD (Injection Locked Frequency Divider) technique is used in the prescaler in order to approach low power design for multi-modulus divider. This frequency synthesizer operates from 9.8GHz to 10.3GHz with single 1.8v supply and consumes 85 mW. The design theory, consideration, simulation and layout will be showing as the following.
A classical digital PLL architecture, which applies for RF system incorporating a digital divider in the feedback path for frequency multiplication, enables the function of channel selection or sigma delta modulation. Although, for the OC-192 it is divide by 16, this thesis proposed prescaler which capable of operating at 10 GHz with continuous output divide ratio. So, the design also focuses on high-speed prescaler, in order to breakthrough the circuit limitation as well as operating frequency. This thesis also proposed the ring oscillator based ILFD which fabricated on TSMC 0.25um CMOS process operating. The modulo-3 and modulo-5 ILFD operated on 7.1GHz and 18.1GHz respectively is also proposed and measured.

關鍵字(中)

★ 除頻器
★ 頻率合成器
★ 鎖相迴路
★ 光纖系統

關鍵字(英)

★ frequency synthesizer
★ PLL
★ divider

論文目次

Abstract 1
Content 2
List of Figures 4
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Thesis Organization 4
Chapter 2 PFD、Charge Pump and Loop Filter 5
2.1 Phase Frequency Detector 5
2.1.1 Basic Phase Frequency Detector 5
2.1.2 Reformed PFD 6
2.2 Charge Pump 8
Chapter 3 Voltage Control Oscillator 11
3.1 General Considerations 12
3.2 Phase noise 13
3.2.1 Leeson’s Formula 14
3.2.1.1 Q of an oscillator 14
3.2.1.2 Phase Noise Mechanisms 19
3.2.1.3 Waveform Symmetry Properties 21
3.3 Dual Loop LC-VCO 22
3.4 Switched Tuning Technique 24
3.5 VCO Schematic 30
3.6 Simulation Result 31
Chapter 4 Multi-Modulus Divider 32
4.1 Architectural Approach 32
4.2 Prescaler 34
4.2.1 Introduction 34
4.2.2 Superharmonic ILFD 35
4.2.2.1 Introduction 36
4.2.2.2 Injection locked frequency divider architecture 38
4.2.2.3 Modulo-3 Frequency Divider 40
4.2.2.4 Modulo-5 Frequency Divider 41
4.2.2.5 Experimental results 42
4.2.2.6 Modulo-4 Frequency Divider 50
4.2.3 High Divide Ratio Multi-Phase ILFD 51
4.2.4 Phase Rotate Mechanism 53
4.3 Programmable Counter and Swallow Counter 57
Chapter 5 Conclusion 59
Reference 61

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指導教授

陳巍仁(Wei-Zen Chen)

審核日期

2002-7-16

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