探討分離式簡化電路模型在半導體元件模擬上的效益

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姓名

李嘉文(Jia-Wen Lee) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

探討分離式簡化電路模型在半導體元件模擬上的效益
(A simplified Circuit Model for Decoupled Method in Semiconductor Device Simulation)

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摘要(中)

本論文探討使用較為節省記憶體空間的分離法等效電路在半導體元件模擬上的效益。分離法分離我們所使用半導體上的三組等效電路並且依序計算處理，三組等效電路是由三個描述半導體電性的偏微方方程式所轉換而成。透過模擬雙載子電晶體及金氧半場效電晶體來比較分離法與聯合法的計算效率及準確性，結果顯示分離法使用較少的記憶體空間，是聯合法的九分之一，而且得到的模擬結果是相同的，在模擬金氧半場效電晶體的次臨限電壓區域，及雙載子電晶體的低注入區域的電壓電流時，分離法比聯合法有較快的速度。在混階模擬方面，我們也提出部分分離法，它具有聯合法九分之四的記憶體空間，而且擁有完整的邊界條件可用於混階模擬上。

摘要(英)

In this thesis, we study the decoupled method which requires less memory on semiconductor device simulation. The decoupled method decoupled the three equivalent circuits of semiconductor and solved them sequentially. The three equivalent circuits are formed by formulating the three partial differential equations which describe the electrical behavior of semiconductor. The decoupled method is compared by coupled method for computational efficiency and accuracy in simulation of BJT and MOSFET. Results show the decoupled method uses one-ninth memory space of the coupled method. The simulation results are identical. Decoupled method are faster than coupled method when simulating in subthreshold region of MOSFET and low level injection of BJT. In mixed-level simulation, we propose a compromising partial decoupled method which requires four-ninths memory space of the coupled method and has complete boundary condition for mixed-level simulation.

關鍵字(中)

★ 使用分離法在半導體元件模擬

關鍵字(英)

★ decoupled method in semiconductor device simulat

論文目次

chapter 1.Introduction...........................................1
chapter 2.Decoupled Method.......................................3
2.1 Introduction to decoupled method.....................3
2.2 Difference between decoupled and coupled method......5
2.3 Equivalent circuit model for decoupled method........8
2.4 Band solver..........................................14
chapter 3.Comparison of Decoupled and Coupled Method.............17
3.1 Verification of BJT numerical simulation.............17
3.2 Verification of MOSFET numerical simulation..........26
3.3 Discussion and comments..............................31
chapter 4.Partial Decoupled Method...............................32
4.1 Partial decoupled method.............................32
4.2 BJT numerical simulation with partial decoupled method..34
4.2 Mixed-level simulation with partial decoupled method....37
chapter 5.Conclusion.............................................40

參考文獻

[1]H. K. Gummel, “A self-consistent iterative scheme for one-dimensional steady state transistor calculations,” IEEE Trans. Electron Devices, vol. ED-11, pp.455-465, 1964.
[2]S. Selberherr, Analysis and Simulation of Semiconductor Devices. New York: Springer, 1984.
[3]K. Mayaram and D. O. Pederson, “Coupling Algorithms for Mixed-level Circuit and Device Simulation,” IEEE Transactions on computer-aided design, vol. 11, no. 8, pp. 1003-1010, 1992.
[4]C.-L. Teng, “An Equivalent Circuit Approach to Mixed-Level Device And Circuit Simulation,” M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, Jun. 1997.
[5]C. C. Chang, “Verification of 1D BJT Numerical Simulation and its Application to Mixed-level Device and Circuit Simulation,” M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, Jun. 2001.
[6]S. Dimitrijev, Understanding Semiconductor Devices. Oxford University Press, 1997.
[7]M. S. Obrecht, K.-C. Wu, R. W. Dutton, E. L. Heasell, and M. I. Elmasry, “Further Improvement in Decoupled Methods for Semiconductor Device Modeling,” in Proc. NUPAD V Conf., pp. 129-132, June 1994.
[8]M. S. Obrecht, Mohamed I. Elmasry, Edwin L. Heasell, “TRASIM: Compact and Efficient Two-Dimensional Transient Simulation for Arbitrary Planar Semiconductor Devices,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 4, pp.447-458, April 1995.

指導教授

蔡曜聰(Yao-Tsung Tsai)

審核日期

2002-6-27

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