博碩士論文 89521079 詳細資訊

姓名 柯宏親(Hung-Chin Ke)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 先進加密標準演算法之IP模組元件設計與驗證
(IP reuse design and Verification for Advance Encryption Standard algorithm)
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摘要(中) 為了要加速系統晶片之設計,智產設計之再利用(IP reuse)成為必需之工具及技術,本論文針對Advance Encryption Standard (AES) 演算法的特性,利用IP reuse 的概念去設計出一個高效率的128位元的區塊加密器(AECs),這個加密器之throughput 可以逹到1163Mb/s,我們採用加解密核心分開設計,以增加系統的彈性並利用平行處理的架構和回授電路的設計,有效可以加快加解密速度和降低硬體的複雜度並設計一個 4 clocks 存取的移位暫存器去減少I/O pins 接腳數,以致不會造成成本之浪費.
我們利用VHDL,Synplify,ModelSim,MaxplusII,and Quartus II來設計,合成及模擬AECs,最後使用Field Programmable Gate Array(FPGA)來實現,其加密核心之Logic element(LE)總數為1437,其工作頻率為100MHz,資料處理量約為1163Mbps,解密核心之LE總數為1895個,其工作頻率為90MHz,資料處理量為900Mb/s,根據此特性應用在影像來逹成加解密的效果.
摘要(英) In order to speed up the pace of system on a chip (SOC) development, designers intend to integrate intellectual properties (IP) into the chip. IP in chip design industry refers to pre-designed and pre-verified building blocks that can be reused for faster time-to-market. In this thesis, the research is focus on the characteristic of Advance Encryption Standard (AES). Using the IP reuse concept of AES to implement the 128bits block cipher efficiently and increase flexibility of Encryptor / Decryptor, we design Encryption Core and Decryption Core separately. Moreover, because the AES algorithm is the iterative encryption algorithm, we just only design one encryption/decryption architecture, pipeline architecture and using the feedback circuit to reduce the hardware complexity. In order to reduce the I/O pins, we design the shift register with four clocks cycles imports the Plaintext 128 bits and Secret Key 128 bits.
To realize the AECs, we use VHDL, Synplify, ModelSim, and MaxplusII for designing, synthesizing and simulation. Field Programmable Gate Arrays (FPGAs) are chosen as our target hardware environment. The encryption core design of AECs for area requires 1437 logic cells. The maximum operating clock is 100Mhz and the corresponding data throughput is about 1163Mbit/s. the decryption core design of AECs for area requires 1895 logic cells. The maximum operating clock is 90Mhz and the corresponding data throughput is about 900Mbit/s. According to the characteristic, we can apply to the field of Image encryption.
關鍵字(中) ★ 影像加密
★ 矽智財產權
★ 場控邏輯閘陣列
★ 先進加密標準
關鍵字(英) ★ FPGA
★ Reuse
★ IP
★ Image encryption
論文目次 Contents
Abstract ( In Chinese)
Abstract ( In English)
List of Figures
List of Tables
Chapter 1 Introduction..........................1
1.1 Motivation.................1
1.2 Literature Survey........1
1.3 Aim of the Thesis.......2
1.4 Merit of the Method...2
1.5 Organization of the Thesis...3
Chapter 2 Description of AES algorithm.....4
2.1 General Description......4
2.2 Definition and Notation .....4
2.2.1 Glossary of Terms and Acronyms....5
2.2.2 Algorithm Parameters, Symbols, Terms, and Functions...6
2.2.3 Inputs and Outputs...7
2.2.4 The state, the Cipher Key and the number of rounds..8
2.3 Mathematical preliminaries.......10
2.3.1 Galois Field.......10
2.3.2 Polynomial Addition........10
2.3.3 Polynomial Multiplication.....11
2.3.4 Polynomial multiplication by x ......... 12
2.4 Cipher......12
2.4.1 ByteSub Transform......13
2.4.2 ShiftRow Transform.....15
2.4.3 MixColumn Transform.....16
2.4.4 AddRoundKey Transform.....17
2.5 Key schedule......18
2.5.1 Key expansion....18
2.5.2 Key selection....20
2.6 Inverse Cipher.......21
2.6.1 InvBytesub transform.....21
2.6.2 InvShiftRow transform.....21
2.6.3 InvMixColumn transform....22
2.6.4 AddRoundkey transform....22
2.7 Summary......23
Chapter 3 Implementation of the AES block cipher....25
3.1 AES design strategy.....26
3.2 FPGA architecture of AES block cipher.... 27
3.2.1 The Encryption Core.........27
3.2.1 The Decryption Core........29
3.3 AES Finite State Machine (FSM) Controller......31
3.4 Matlab Implementation of the AES ......32
3.4.1 The Cipher.......32
3.4.2 The Inverse Cipher......33
3.4.3 Key expansion..... 34
Chapter 4 Analysis and design of AES cipher main macro....35
4.1 IP reuse introduction....35
4.2 Analysis and design of AES cipher main macro....37
4.2.1 Encryption macro...37
4.2.2 Decryption macro....38
4.2.3 Input/Output shift register unit....39
4.2.4 ByteSub/InvByteSub unit design....41
4.2.5 ShiftRow/InvShiftRow unit design ....42
4.2.6 MixColumn/InvMixColumn unit design...44
4.2.7 AddRoundkey unit design...47
4.2.8 ERU and DRU unit design...47
4.2.9 Key schedule unit design... 48
Chapter 5 IP reuse design and verification for AES cipher 51
5.1 Encryption/Decryption core block diagram....51
5.2 Comprehensive technical specification.....53
5.3 Core interface and Pins description....53
5.3.1 AES interface....56
5.3.2 AES controller...58
5.4 Integration of key macro....59
5.5 Cad tools and environment.....60
5.6 AES timing simulation......62
Chapter 6 Conclusion and Future work...69
Appendix A – Altera Apex20KC device...73
Appendix B – Cipher Example....75
Appendix C – Matlab implementation of the AES cipher...77
and inverse cipher
Appendix D – Enhancing Compression and Encryption.....81
of image with FPGA-based Cryptosystems
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Altera FPGA”, May, 2000 http://csrc.nist.gov/encryption/aes/round2/pubcmnts.htm
[9] AES home page: http://www.nist.gov/aes/.
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[28] Said, A.; Pearlman, W.A.,” A new, fast, and efficient image codec based on set partitioning in hierarchical trees”, Circuits and Systems for Video Technology, IEEE Transactions on Volume: 6 Issue: 3 , June 1996 Page(s): 243 –250.
[29] Jan-Ruei Lin, “Design of Encryption Chips Using the Blowfish Algorithm,” Master Thesis, Central University, 2000.
[30] Pei-Jung Wu“VLSI Implementation and IP Design for Advanced Encryption standard”,Master Thesis, Tung Hwa University 2001.
[31] Yeh, Bi-Yun, “IP-Based Chip Design Methodology”,Matster Thesis, Taiwan University,1996
指導教授 歐石鏡(Shih-Ching Ou) 審核日期 2002-6-5
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