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姓名	徐禮弘(Li-Hung Shiu)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	使用FPGA晶片發展一個雕塑曲面設計 (Using FPGA Chip to Develop Sculpture Surfaces Design)
相關論文	★ 二維電場微風計之設計與實作 ★ FPGA之電磁波量測儀的設計與實作 ★ 在虛擬環境中發展一整合式電腦繪圖系統- Case Study of Bezier, B-Spline and NURBS Algorithms ★ α-spline與NURBS雕塑曲面設計之研究 ★ 利用Blowfish演算法於加密晶片之設計 ★ 先進加密標準演算法之IP模組元件設計與驗證 ★ 應用Java技術結合無線網路之設計與實作 ★ 使用FPGA 實現一串流加密模組之 設計與驗證 ★ e-Learning 多媒體教材之實作研究 ★ 利用3D分子模擬軟體預測竹筍蛋白質相似結構及功能 ★ 使用最小能量原理來改進電腦輔助藥物設計中的分子對接技術之研究 ★ 系統理論在生物資訊之應用
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摘要(中)	OpenGL在現在的3D繪圖上佔了重要的地位，舉凡電腦遊戲、軍用模擬程式、或科學視覺化或大型資料庫的視覺化應用，都被拿來作廣泛的使用，其中的原因也是因為OpenGL(Open Graphics Library)開放的標準，使得程式設計師可以用得更為順手。最近幾年由於硬體晶片在速度及技術上的快速發展，使得原本昂貴的 OpenGL 3D 繪圖卡變得一般使用者可以負擔得起，甚至一些較便宜的卡成為購買電腦時的標準配備；是以不僅在專業與消費市場上，OpenGL都有不可忽視的前景。而FPGA(Field Programmable Gate Array)在現今技術的進步下可在一顆晶片上裝入更多的邏輯閘，同時有更快的執行速度。 本論文提出一個依據NURBS(Non-Uniform Rational B-Spline)演算法為架構的3D繪圖晶片(NGC, NURBS Graphics Chip)，此晶片可做為微處理器的周邊裝置，使用者可以用此晶片繪出精度為16 bits的曲線及曲面。在論文中，首先描述整個系統的架構組成，再針對FPGA做硬體的介紹及原理說明。其次說明NURBS曲面造形演算法，並以程式語言Visual C++及OpenGL模擬驗證其效果，接著並以VHDL及Maxplus Ⅱ加以模組化設計，並完成電路的模擬、佈局，最後將程式下載於FPGA晶片中。而所設計的晶片型號為EPF10K100ARC240-1，大約使用了3,900個logic cells，其推論速度可達15 MHz。未來計畫利用Microsoft Visual C++ 6.0及OpenGL繪圖函式庫來連結此晶片以展示其立體物件從而達到在3D環境下作業的要求，並且加上插入/刪除節點、改變控制點位置/權重等基本弁遄A及如燈光、透視投影及資料庫等進階弁遄C
摘要(英)	OpenGL(Open Graphics Library) is a three-dimensional computer graphics API (Application Program Interface) and it is important to apply in the field of computer game, military sham program, and vision of scientific with large database. One of the reasons is that OpneGL has open standard and can it make programmers use the API can be easily. The original price of hardware version of OpenGL 3D was expensive, but due to the speed and the technology of hardware chip fast development, now general consumers can be afford the product. In addition, some inexpensive one becomes standard device when people buy computer. Therefore the prospects of OpenGL are expectable. Because the technology nowadays is becoming more and more advanced, FPGA can assemble more logic gates into one chip. Furthermore, it has faster speed to operate structured system. The aim of the thesis is to propose a three-dimensional graphics chip NGC (NURBS Graphics Chip), in accordance with the NURBS algorithm the chip was structured. This chip, which has 16 bits precision, can apply to peripheral device of computer, and user can use it for fitting curves and surfaces. In this thesis, we first describe the framework of whole system, then introduce the hardware of FPGA and explain the principle. Secondly, we will also illustrate the NURBS and B-Spline algorithms, and to precede it’s testing and verifying via using Visual C++ and OpenGL. Besides, using VHDL (Very high speed integrated circuit Hardware Description Language) and Maxplus II tools to design the system model. Finally, we finish the simulation and the layout, and then download the program into chip, which is EPF10K100ARC240-1. We use about 3900 logic cells, and the clock of system is 50MHz.
關鍵字(中)	★ 電腦繪圖	關鍵字(英)	★ FPGA ★ B-Spline ★ NURBS ★ VHDL ★ graphics
論文目次	Abstract (in Chinese) Abstract (in English) Acknowledgments List of figures List of tables Chapter 1 Introduction 1.1 Introduction 1.2 Literature Survey 1.3 Aim of the Thesis 1.4 Merit of the Method 1.5 Organization of the Thesis Chapter 2 General Description of FPGA 2.1 Overview of the FPGA 2.2 The SRAM based FPGA 2.3 The Framework of the FPGA 2.3.1 Configurable Logic Blocks 2.3.2 Input/Output Blocks 2.3.3 Connections 2.4 The Design flow of FPGA Chapter 3 Complex Curves and Surfaces 3.1 Introduction 3.2 Bezier Curves and Surfaces 3.2.1 Bezier Curves 3.2.2 More on Bezier Curves 3.2.3 Bezier Surfaces 3.3 B-Spline Curves and Surfaces 3.3.1 B-Spline Curves 3.3.2 Basis Functions 3.3.3 B-Spline Surfaces 3.4 NURBS Curves and Surfaces 3.4.1 NURBS Curves 3.4.2 NURBS Surfaces Chapter 4 Using FPGA for Realizing the NURBS Algorithm 4.1 The Architecture of ICGW 4.2 The Block of ICGW 4.3 Realizing graphic algorithms 4.3.1 Spreading Knot Vector 4.3.2 Generating basis function equation 4.3.3 Evaluating basis functions into memory 4.3.4 Basis function generator 4.3.5 NURBS Surface 4.3.6 B-Spline Curve 4.3.7 B-Spline Surface 4.4 Chip Flow Chart Chapter 5 Hardware Implementation 5.1 Register 5.2 Knot Vector Gauger 5.3 Basis Function Generator 5.3.1 Elements Generator 5.3.2 Basis Function Generator 5.4 Curve Point Generator 5.5 Controller 5.6 Example 5.6.1 Simulating NURBS Curve 5.6.2 Simulating NURBS Surface 5.7 Performance Comparison Chapter 6 Conclusions and Future work 6.1 Conclusions 6.2 Future work ReferencesAppendix -- Development of a Computer Aided Geometric Design System Based on FPGA Technology
參考文獻	[1] Les. Piegl, Wayne. Tiller, “The NURBS Book”, 2nd edn. Ed. Springer, 1997. [2] David F. Rogers, J. Alam Adams, “Mathematical Elements for Computer Graphics”, 2nd. [3] A. Edward, “Interactive computer graphics: a top-down approach with OpenGL”, Addison-Wesley, 1997. [4] Ibrahim Zeid, “CAD/CAM Theory and Practice”. [5] Alan Watt, “3D Computer Graphics”, 3nd. [6] F.S.S, “Computer-Aided Geometry Design & Non-Uniform Rational B-Spline (CAGD & NURBS)”, 1994. [7] Mason Woo, Jackie Neider, Tom Davis, “OpenGL Programming Guide”, 2nd, 1997. [8] C. de Boor, “The numerical evaluation of B-Spline”, Jour. Inst. Math. Applic., Vol. 10, pp.134-149, 1972. [9] Richard S. Wright, Jr. Michael Sweet, “OpenGL Super Bible”, 2nd, 1999. [10]Sanchez-Reyes, J., “A Simple Technique for NURBS Shape Modification”, IEEE Computer Graphics and Applications, 17 1997 52-59. [11]C. de Boor, “A Practical Guide to Splines” Applied Mathematical Sciences, Vol. 27, 1977. [12]Kaihuai Qin, Wenping Wang, Zesheng Tang, “Representing Spheres and Ellipsoids Using Periodic NURBS Surfaces with Fewer Control Vertices”. [13]Dong – Ying Lin, “The Design and Implementation of a Non-Uniform Rational B-Spline curve and surface chip”, 1999. [14]Imre Juhasz, “Weight-based shape modification of NURBS curves”, Computer Aided Geometric Design 16 1999 377-383. [15]M. Gopi and S. Manohar, “A unified architecture for the computation of B- Spline curve and surfaces”, IEEE Tran. On Parallel and Distributed System, Vol. 8, no. 12, pp. 1275-1287, Dec. 1997. [16]P.N. Mallon, M. Boo, J.D. Bruguera, “Parallel Architecture for Conversion of NURBS Curves to Bezier Curves”, Department of Electronic and Computer Engineering, 2000. [17]P.N. Mallon, M. Boo, J.D. Bruguera, “Minimum Latency NURBS to Bezier Converter”, Department of Electronic and Computer Engineering, 2001. [18]“FLEX 10K Embedded Programmable Logic Device Family.pdf”, http://www.altera.com/ [19]E. Mortenson, “Geometric modeling”, John Wiley & Sons, 1985. [20]http://www.cee.hw.ac.uk/~ian/hyper00/contents.html [21]http://www.vcc.com/fpga.html#anchor783339
指導教授	歐石鏡(Shih-Ching Ou)	審核日期	2002-6-6
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