元件分割法及其在二維互補式金氧半導體元件之模擬

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：11

、訪客IP：13.59.36.203

姓名

林峰濰(Feng-Wei Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

元件分割法及其在二維互補式金氧半導體元件之模擬
(Device-partition method and its application to 2-D CMOS device simulation)

相關論文

★ 表面電漿共振效應於光奈米元件之數值研究	★ 金氧半電容元件的暫態模擬之數值量測
★ 雙載子電晶體在一維和二維空間上模擬的比較	★ 改善後的階層化不完全LU法及其在二維半導體元件模擬上的應用
★ 一維雙載子接面電晶體數值模擬之驗證及其在元件與電路混階模擬之應用	★ 階層化不完全LU法及其在準靜態金氧半場效電晶體電容模擬上的應用
★ 探討分離式簡化電路模型在半導體元件模擬上的效益	★ 撞擊游離的等效電路模型與其在半導體元件模擬上之應用
★ 二維半導體元件模擬的電流和電場分析	★ 三維半導體元件模擬器之開發及SOI MOSFET特性分析
★ 含改良型L-ILU解法器及PDM電路表述之二維及三維元件數值模擬器之開發	★ 含費米積分之高效率載子解析模型及其在元件模擬上的應用
★ 量子力學等效電路模型之建立及其對元件模擬之探討	★ 適用於二維及三維半導體元件模擬的可調變式元件切割法
★ 整合式的混階模擬器之開發及其在振盪電路上的應用	★ 用時域模擬法探討S參數及其應用

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

本論文主要是要探討如何有效的去節省在模擬半導體時所需的記憶體空間，我們開發了四種不同的方法去模擬半導體元件。第一種方法是聯合法，，此種方法所需的記憶體空間在所有的方法裡面是最大的。第二種方法是部分分離法，此種方法所需的記憶體空間會比聯合法小。最後我們開發了元件分割法，此種方法可區分為二個不同的模式，分別為部分重疊和非部分重疊，元件分割法的優點是我們執行程式時將不會再受限於記憶體的空間。我們將會用上述的這幾種方法去模擬n型通道的金氧半場效電晶體，並比較它們模擬的結果，最後我們將使用這些方法去模擬互補式金氧半導體並且比較它們模擬的結果。

摘要(英)

In this thesis, we focus on how to effectively save required memory space when simulate a semiconductor device. We develop four different methods to simulate semiconductor devices. First method is coupled method(CM). It requires biggest memory space in all of the methods. Second method is partial decoupled method(PDM). The memory space with PDM is less than CM. Last, we develop device-partition method. It can be divided into two different modes. One is overlapped mode, the other is unoverlapped mode. The advantage of device-partition method is that our program can be compiled without limitation by memory space. We will use these methods to simulate an n-channel MOSFET and compare simulation result. Finally, we will use these methods to simulate a CMOS circuit and compare simulation result also.

關鍵字(中)

★ 分割

關鍵字(英)

★ divide

論文目次

1. Introduction………………………………..…………………..……………….1
2. Memory Reduction in Device Simulation………………………………….3
2.1 Introduction………………………………………………….………………3
2.2 Coupled Method……………………………………………….…………….5
2.3 2-D Equivalent Circuit………………………………………….……………7
2.4 Partial Decoupled Method…………………………………………………..10
2.5 Band Solver…………………………………………………………………12
2.6 MOSFET Simulation Result with CM and PDM Method………………..14
3. Device-partition method…………………………………………………….17
3.1 Device-partition Method with Overlapped Mode……………….………….17
3.2 Device-partition Method with Unoverlapped Mode………….…………….19
3.3 Unoverlapped Mode with three-part Partition…...…………………...……..23
3.4 MOSFET Simulation Result with Device-partition Method………………26
4. 2-D CMOS Device simulation……………………………………………...30
4.1 Introduction to CMOS Characteristic and Structure……..………………30
4.2 CMOS Transfer-characteristic simulation……………….………………..34
4.3 Simulation in CMOS Propagation Delay Time….…………………...……37
5. Conclusion……………………………………………………………………...41
List of figures
2.1 Device grid diagram.……………………...…...…………………………………..4
2.2 Sketchy diagram of memory space.……………...………………………………..5
2.3 Flowchart of coupled method…………………………………………………….6
2.4 A rectangular mesh in two-dimensional simulation.………………………………7
2.5 The equivalent circuit of Poisson’s equation.………………..………………….8
2.6 The equivalent circuit for electron continuity equation.……………………….….9
2.7. The equivalent circuit for hole continuity equation.……………………………10
2.8 Flowchart of partial coupled method.…………………………………..………11
2.9. The diagram of band matrix.………………………………………………..…12
2.10 Bandwidth of interleaving method.………………….……………………..…13
2.11 Comparison of matrix size in CM and PDM.…………………………………...14
2.12 MOSFET structure diagram.……………………………………………………14
2.13 VDS-ID curve with 10 channel length.……………….…………………..15
2.14 VDS-ID curve with 1 channel length.…………………………………….16
2.15 Transfer characteristic of MOSFET with 1 channel length.……………….16
3.1 Dividing device into two parts with overlapped mode.…………………………..18
3.2 The flowchart of device-partition method.…………………………………….18
3.3. Dividing device into two parts with unoverlapped mode.……………………….20
3.4. The equivalent circuit of Poisson’s equation in 1st part.……………………….21
3.5. The equivalent circuit of electron continuity equation in 1st part.……………...21
3.6. The equivalent circuit of hole continuity equation in 1st part.………………….21
3.7. The equivalent circuit of Poisson’s equation in 2nd part.……………….………22
3.8. The equivalent circuit of electron continuity equation in 2nd part.…….……….22
3.9. The equivalent circuit of hole continuity equation in 2nd part.……….……...22
3.10 Dividing device into three parts with unoverlapped mode.……………………24
3.11. The flowchart of dividing device into three parts.……………………………25
3.12 ID-VDS curves for the MOSFET with overlapped mode.…………..……….27
3.13 ID-VDS curves for the MOSFET with unoverlapped mode and two-part partition………………………………………………………………………...27
3.14 ID-VDS curves for the MOSFET with unoverlapped mode and three-part partition.………….…………………………………………………………….28
3.15 Comparison of the CPU time for all of the methods…………………………...29
4.1 CMOS inverter…………………………………………………………………...31
4.2 CMOS DC transfer characteristic and operating regions.………………………..31
4.3 CMOS n-well process……………………………………………………………33
4.4 CMOS p-well process……………………………………………………………33
4.5 CMOS twin-tub process……………………………………………………….…33
4.6. CMOS structure.…………………………………………………………….…34
4.7 DC transfer characteristics for CM and PDM.………………………...…………35
4.8 DC transfer characteristics for CM and Unoverlapped_3parts…………………..35
4.9 Transfer-characteristic dependence on the ratio .………………….36
4.10 The delay-time definition of a typical inverter.……………….………………...37
4.11 The waveforms for output voltage and input voltage.……………………..…..38
4.12 The waveform dependence of output voltage on …..………………………39
List of tables
3.1 Memory space required by different methods.………………………………….26
4.1 Each region of CMOS.…………………………………………………………...32
4.2 Comparison of CMOS propagation delay time......………………………………40

參考文獻

[1] J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design, Van Nostrand Reinhold, p. 427 ,1994.
[2] A. R., Brown, A. Asenov, S. Roy and J. R. Barker, “Development of a parallel 3D finite element power semiconductor device simulator”, IEE Colloquium, Physical Modelling of Semiconductor Devices, 1995.
[3] K. Mayaram and D. O. Pederson, “Coupling algorithms for mixed-level circuit and device simulation, IEEE Transactions on computer-aided design, vol. 11, no. 8, pp. 1003-1010, 1992.
[4] C.-L. Teng, “An equivalent circuit approach to mixed-level device and circuit simulation,” M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, Jun. 1997.
[5] J. W. Lee, “An equivalent circuit model for decoupled method in semiconductor device simulation”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, Jun. 2002.
[6] S. M. Sze, Semiconductor Devices Physis and Technology, Murry Hill, p. 493, 1985.
[7] J. Y. Chen, CMOS Device and Technology for VLSI, Prentice Hall Englewood Cliffs, pp. 164, 1990.
[8] S. Bhattacharya, S. Banerjee, J. Lee, A. Tasch, and A. Chatterjee, “Design issues for achieving latchup-free, deep trench-isolation, bulk, non-epitaxial, submicron CMOS”, Electron Devices Meeting, 1990. Technical Digest., International ,pp. 185-188, 1990.
[9] N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, p. 68 and p.183, 1993.
[10] S.-M. Kang and Y. Leblebici, CMOS Digital Interated Circuits Analysis and Design, McGRAW-HALL, p. 206 and p. 210, 1996.

指導教授

蔡曜聰(Yao-Tsung Tsai)

審核日期

2003-6-22

推文