博碩士論文 90521050 詳細資訊


姓名 游爵豪(Jue-Hao You)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 適用於OC-192收發機之頻率合成器和時脈與資料回復電路
(Clock Multiplier Unit and Data/Clock Recovery for OC-192 Transceiver)
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 目前光纖網路應用在高速和長程傳輸通訊已經變成一個主要的趨勢。今日,高速率光纖傳輸標準主要是依循SONET標準。骨幹網路中OC-192 SONET的傳輸速率接近10Gbps,該速率可望很快在骨幹網路中普及並應用在終端網路之中。同時隨著高速光纖傳輸網的推廣,每個關鍵元件的價格與功率開始受到關注,高頻寬光通訊網路的一個關鍵元件是收發機。我們的目的便在於開發適用於SONET OC-192收發器之時脈產生電路和時脈與資料回復電路。在傳送端,經過編碼的資料信號需經由多工器將低速之並列信號轉成一高速串列信號,因此需一時脈產生電路產生所需之高速時脈信號對信號源取樣。在接收端,資料與時脈回復電路必須擷取NRZ信號之頻率與相位,並據此產生精準之時脈信號以對輸入信號進行取樣,以降低接收信號之錯誤產生率。
時脈產生電路之主要實現方式為鎖相迴路式之頻率合成器,主要目的在提供多工器一個資料取樣之參考信號源,其功能依據SONET OC-192所確立之標準,由一622.08MHz本地振盪源經頻率合成達到一9.9533GHz之輸出參考信號。同時為達到廣泛之應用,壓控振盪器之輸出頻段將包含在10Gb/s附近之各種通訊標準。此電路採用TSMC 0.35μm SiGe BiCMOS製程技術,操作電壓為3.3V。其中一個單獨之10GHz除頻器已經由設計並驗證可操作頻段為500MHz ~ 9.1GHz,晶片面積約1毫米×0.8毫米,同時消耗功率78.7毫瓦。此除頻器將可應用於產生降頻之時脈信號,以作為序列至並列信號轉換與解多工器之用,或應用於10GHz之頻率合成器。本論文所提出之頻率合成器為全差動式,具有改善相位雜訊與排除電源雜訊之優點。其晶片面積約2毫米×1毫米,同時消耗功率230.4毫瓦。
鎖相迴路式資料回復電路兼具高頻操作與易於積體電路化之優點,同時可藉由相頻偵測器之自我修正達成時脈與資料之自行校準到位,因此傳統上高頻之資料與時脈回復電路多採鎖相迴路式架構。本論文實現一個無須參考信號之鎖相迴路式高速時脈與資料回復電路。本電路使用二位元式相位比較器,因此傳統鎖相迴路線性模型將不適於此。一個適用於二位元式資料與時脈回復電路之線性模型在本論文中提出,藉此設計一個符合SONET OC-192所規定雜訊抖動標準之資料與時脈回復電路。此電路亦採用TSMC 0.35μm SiGe BiCMOS製程技術,操作電壓為3.3V。其架構為全差動式,同時輸出頻段也將包含在10Gb/s附近之各種通訊標準。系統之迴路頻寬為4.18MHz、抖動峰值為0dB、抖動產生的峰對峰值約為5ps,達到OC-192所規定雜訊抖動標準,整體晶片消耗功率約589.1毫瓦。
摘要(英) The optical network applies in the high-speed and long-haul communications has become a major trend presently. Today, the highest speed for wired data communication is reached using optical fiber transmission operating in accordance with the SONET (Synchronous Optical Networking Standards) standards. The data rate of the SONET OC-192 is close to 10Gb/s and it expects that the data rate of 10Gb/s will be universal in backbone network and applied in terminal networks. And the transceiver is the critical device in high-speed optical networks. The goal in the thesis is to develop a clock multiplier unit and clock/data recovery circuit that suit to the SNOCT OC-192 transceiver. At the transmitter end, the encoded parallel data must be transformed into serial signals by MUX and therefore a CMU is needed to generate a high-speed reference signal for parallel-to-serial data conversion and multiplexing. At the receiver end, a CDR circuit derives the input frequency and phase of the NRZ signals and generates a high precision clock to sample the incoming data so as to reduce the bit error rate.
Clock multiplier Unit is accomplished by using PLL-based frequency synthesizer. The main goal is to generate a reference signal for multiplexer. Its function is to synthesize a 9.9533GHz output signal form a 622.08MHz reference source according to the SONET OC-192 standard. For various applications, the output frequency range of the oscillator covers that of various communication standards around 10Gb/s. The CMU circuit is fabricated in TSMC 0.35μm BiCMOS process and its operation voltage is 3.3V. An individual chip of 16:1 static frequency divider has been designed and demonstrated. Its operation range is 500 MHz ~ 9.1 GHz, chip size is 1 × 0.8 mm2, and power consumption is 78.7mW. It can be used to generate down-frequency clock signals for demultiplexer and used in frequency synthesizer. A fully differential clock multiplier unit presented in the thesis achieves improved levels of phase noise and supply rejection performance through the use of fully differential architecture. The CMU has a die size of 2.1 × 1.1 mm2 and consumes 230.4mW from 3.3 V.
PLL-based CDRs are benefited from capabilities of high frequency operation and feasibility for monolithic integration. Moreover, the phase frequency detector can adjust the transition edge of the sampling clock and align to that of the input data. Therefore, conventionally, high frequency clock and data recovery circuits are of PLL based type. A PLL-based high-speed CDR circuit without reference signals is achieved in this thesis. Because the phase detector used in the CDR is binary type, the conventional linear model of the PLL does not fit it. A novel analytical linear model for the binary type CDR circuit is addressed. Then a CDR circuit that conforms to the SONET OC-192 jitter requirements is designed by it. The CDR circuit is fabricated in TSMC 0.35μm BiCMOS process and its operation voltage is 3.3V. The architecture of it is fully differential and the output frequency range covers that of various communication standards around 10Gb/s. Finally, the jitter bandwidth is 4.18MHz, jitter peaking is 0dB, and the jitter generation is about 5ps. The jitter performances of it suit the OC-192 jitter requirements and its power consumption is 589.1mW.
關鍵字(中) ★ 時脈與資料回復電路
★ 頻率合成器
關鍵字(英) ★ CDR
★ transceiver
★ CMU
★ OC-192
論文目次 Content
Abstract i
Content iii
List of Figures vii
List of Tables x
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Research Goals 3
1.3 Thesis Organization 5
1.4 References 6
Chapter 2 Frequency Synthesizer and Clock/Data Recovery in Optical Fiber Systems 8
2.1 Introduction 8
2.2 Transmitter and Receiver Architecture 9
2.2.1 Transmitter 9
2.2.2 Receiver 10
2.3 Frequency Synthesizer 12
2.3.1 Role of Frequency Synthesizer 12
2.3.2 Phase Noise 13
2.3.3 Spurious Tones 14
2.4 Clock and Data Recovery 14
2.4.1 Role of Clock and Data Recovery 15
2.4.2 PLL-Based CDR Circuit 16
2.4.3 Over-sampling-Based Data Recovery 17
2.4.4 Summary 18
2.5 Summary 19
2.6 Reference 19
Chapter 3 A 10GHz Fully-Differential Frequency Synthesizer 21
3.1 Introduction 21
3.2 Phase Looked Loop Fundamentals 22
3.2.1 Phase Locked Loop Fundamental 22
3.2.2 Frequency Synthesizer Architecture 23
3.3 PLL Linear Model 24
3.4 Voltage-Controlled Voltage 26
3.4.1 The principle of the LC-tank VCO 27
3.4.2 Inductor 28
3.4.3 Switching Tuning Mechanism 29
3.4.4 VCO Topology and Simulation Results 30
3.5 16:1 Frequency Divider 32
3.5.1 Two Types of the Digital Frequency Divider 32
3.5.2 Design Method for Low Power Consumption 33
3.5.3 Circuit Implementation 36
3.5.4 Summary 40
3.6 Other Circuitry Design 41
3.6.1 Phase/Frequency Detector 41
3.6.2 Charge Pump 43
3.6.3 Loop Filter 44
3.6.4 Output Buffer 46
3.6.5 Bias Circuit 46
3.7 Simulation and Experimental Results 48
3.7.1 Chip Overview 48
3.7.2 Simulation 49
3.7.3 Layout 51
3.7.4 Measurement Results 53
3.8 Summary 56
3.9 References 57
Chapter 4 Jitter Analysis for PLL-Based CDR Circuit 60
4.1 Introduction 60
4.2 The Reasons for Jitter Production 61
4.2.1 Noise 61
4.2.2 Data Randomness 61
4.2.3 Pattern-Dependant Jitter 62
4.3 The Basic Jitter Requirement for SONET OC-192 62
4.3.1 Jitter Generation 63
4.3.2 Jitter Transfer 63
4.3.3 Jitter Tolerance 64
4.4 Jitter Analysis in Linear PLL-Based CDR 65
4.4.1 Jitter Transfer Analysis 65
4.4.2 Jitter Tolerance Theory and Analysis 67
4.4.3 Jitter Generation 76
4.5 Summary 76
4.6 Reference 76
Chapter 5 A 10Gb/s Clock and Data Recovery Circuit Without Frequency Acquisition 78
5.1 Introduction 78
5.2 Clock and Data Recovery Fundamentals 79
5.2.1 The work of CDR in Receivers 79
5.2.2 NRZ Data Input 80
5.2.3 Phase-Locking CDR Architecture 81
5.3 The CDR Architecture without Reference Clock 83
5.4 Jitter Analysis for Binary CDR Loop 84
5.5 Phase and Frequency Detector 88
5.5.1 Phase/Frequency Detector Architecture 88
5.5.2 The operation 89
5.5.3 Circuit Design 91
5.5.4 Simulation 93
5.6 Other Circuitry Design 94
5.6.1 Charge Pump and Loop Filter 94
5.6.2 Quadrature-Phase VCO 96
5.6.3 Input Buffer 100
5.6.4 Output Buffer 100
5.6.5 Decision Circuit and Bias Circuit 101
5.7 Simulation Results 102
5.7.1 Chip Overview 102
5.7.2 Simulation 104
5.8 Summary 106
5.9 References 107
Chapter6 Conclusion 109
6.1 Conclusion 109
參考文獻 [1] V. Schwarz, B. Willen, H. Jackel, “56Gbit/s Analogue PLL for Clock Recovery,” IEE Electronics Letters, vol. 37, No. 22, pp. 1336-1338, Oct. 2001.
[2] T. Otsuji et al., “20-40-Gbit/s-Cllass GaAs MESFET Digital Ics for Future Optical Fiber Communications Systems,” International Journal of High Speed Electronics and Systems, vol.9, No. 2, pp. 399-435, 1998.
[3] Z. Lao et al., “20-40 Gbit/s GaAs-HEMT Chip Set for Optical Data Receiver,” International Journal of High Speed Electronics and Systems, vol.9, No. 2, pp. 437-472, 1998.
[4] Ting-Ping Liu, “1.5V 10-12.5GHz Integrated CMOS Oscillators,” VLSI Circuits Design of technical papers, vol.9, No. 2, pp. 55-56, 1999.
[5] A. Tanabe et al., “0.18-μm CMOS 10-Gb/s Multiplexer/Demultiplexer ICs Using Current Mode Logic with Tolerance to Threshold Voltage Function,” IEEE Journal of Solid-State Circuits, vol.36, No. 6, pp. 988-996, 2001.
[6] H. Knapp et al., “25 GHz Static Frequency Divider and 25Gb/s Multiplexer in 0.12μm CMOS,” IEEE ISSCC, pp. 302-303, February 2002.
[7] M. Fukaishi, K. Nakamura et al., “A 20-Gb/s CMOS Multichannel Transmitter and Receiver Chip Set for Ultra-High-Resolution Digital Displays,” IEEE Journal of Solid-State Circuits, vol.35, No. 11, pp. 1611-1618, 2000.
[8] J. Savoj, B. Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit With a Half-Rate Binary Phase/Frequency Detector,” IEEE Journal of Solid-State Circuits, vol.38, No. 1, pp. 13-21, 2003.
[9] Jun Cao, M. Green et al, “OC-192 Transmitter and Receiver in Standard 0.18-μm CMOS,” IEEE Journal of Solid-State Circuits, vol.37, No. 12, pp. 1768-1780, 2002.
[10] Jonathan E. Rogers, and John R. Long, “A 10Gb/s CDR/DEMUX with LC Delay Line VCO in 0.18μm CMOS,” IEEE ISSCC, pp. 254-255, 2002.
[11] Hong-Ih Cong et al., “A 10-Gb/s 16:1 Multuplexer and 10-GHz Clock Synthesizer in 0.25-μm SiGe BiCMOS,” IEEE Journal of Solid-State Circuits, vol.36, No. 12, pp. 1946-1953, Dec. 2000.
[12] M. Meghelli et al., “SiGe BiCMOS 3.3-V Clock and Data Recovery Circuits for 10-Gb/s Serial Transmission System,” IEEE Journal of Solid-State Circuits, vol.35, No. 12, pp. 1992-1995, Dec. 2000.
[13] Y. M. Greshishchev et al., “A Fully Integrated SiGe Receiver IC for 10-Gb/s Data Rate,” IEEE Journal of Solid-State Circuits, vol.35, No. 12, pp. 1949-1957, Dec. 2000.
[14] Y. M. Greshishchev et al., “SiGe Clock and Data Recovery IC with Linear-Type PLL for 10-Gb/s SONET Application,” IEEE Journal of Solid-State Circuits, vol.35, No. 9, pp. 1353-1359, September 2000.
[15] Satoshi Ueno et al., “A Single-Chip 10Gb/s Transceiver LSI using SiGe SOI/BiCMOS,” IEEE ISSCC, September 2001.
[16] G. Georgiou, Y. Baeyens et al., “Clock and Data Recovery IC for 40-Gb/s Fiber-Optical Receiver,” IEEE Journal of Solid-State Circuits, vol.37, No. 9, pp. 1120-1125, September 2002.
[17] M. Meghelli et al., “50-Gb/s SiGe BiCMOS 4:1 Multiplexer and 1:4 Demultiplexer for Serial Communication System,” IEEE Journal of Solid-State Circuits, vol.37, No. 12, pp. 1790-1794, Dec. 2002.
[18] Jafar Savoj, and Behzad Razavi, “High-Speed CMOS Circuit for Optical Receivers,” Kluwer Academic Publishers, 2001.
[19] Dan H. Wolaver, “Phase-Locked Loops Circuits Design,” Advanced Reference Series & Biophysics and Bioengineering Series, Englewood Cliffs, New Jersey 07632: Prentice Hall, 1991.
[20] Roland E. Best, “Phase-Locked Loops: Design, Simulation, and Applications,” New York: McGraw-Hill, Fourth Ed., 1999.
[21] Behzad Razavi, “Design of Integrated Circuits for Optical Communications,” McGraw-Hill Inc., International Edition, 2003.
[22] C. Hogge, “A Self-Correcting Clock Recovery Circuit,” IEEE Journal of Light-wave Technology, vol. LT-3, pp. 1312-1314, December 1985.
[23] J. D. H. Alexander, “Clock Recovery from Random Binary Data,” Electronics Letter, vol. 11, pp. 541-542, Oct. 1975.
[24] C.K. Yang and M.A. Horowitz, “A 0.8-μm CMOS 2.5Gb/s Oversampling Receiver and Transmitter for serial Links,” IEEE JSSC, vol. 31, pp. 2015-2023, Dec. 1996.
[25] Chih-Kong Ken Yang, Ramin Farjad-Rad and Mark A. Horowitz, “A 0.5-μm CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling,” IEEE JSSC, vol. 33, pp. 713-722, May, 1998.
[26] R. E. Best, Phase-Locked Loops: Design, Simulation, and Applications. New York: McGraw-Hill, Fourth Ed., 1999.
[27] Behzad Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, International Ed., 2001.
[28] Behzad Razavi, RF Microelectronics. Prentice-Hall Inc., 1998.
[29] A. Kral, F. Behbahani, and A. A. Abidi, “RF-CMOS Oscillators with Switched Tuning,” IEEE Custom Integrated Circuit Conference, pp. 555-558, 1998.
[30] John W. M. Rogers, Jose A. Macedo, Calvin Plett, “The effect of Varactor Nonlinearity on the Phase Noise of Completely Integrated VCOs,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 9,pp. 1360-1367, September 2000.
[31] L. Lin, L. Tee, and P. R. Gray, “A 1.4-GHz Differential Low-Noise CMOS Frequency Synthesizer Using a Wideband PLL Architecture,” ISSCC Dig. Of Tech. Papers, pp. 204-205, Feb. 2000.
[32] Alioto, M., Palumbo, G., “CML and ECL: optimized design and comparison,” Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on, Volume: 46 Issue: 11, pp. 1330-1341, Nov. 1999.
[33] Ritzberyer, G.; Bock, J.; Knapp, H.; Treitinger, L.; Scholtz, A.L., “38 GHz low-power static frequency divider in sige bipolar technology,” Circuits and Systems, IEEE International Symposium, Volume: 4, pp. 413-416, 2002.
[34] Knapp, H.; Wilhelm, W.; Wurzer, M., “A low-power 15-GHz frequency divider in a 0.8-/spl mu/m silicon bipolar technology,” Microwave Theory and Techniques, IEEE Transactions, Volume: 48 Issue: 2, pp. 205-208, Feb. 2000.
[35] Alioto, M.; Palumbo, G, “Modeling and optimized design of current mode MUX/XOR and D flip-flop,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, Volume: 47 Issue: 5, pp. 452–461, May 2000.
[36] Alioto, M.; Di Cataldo, G.; Palumbo, G., “Design of low-power high-speed bipolar frequency dividers,” Electronics Letters, Volume: 38 Issue: 4, pp. 158–160, Feb. 2002.
[37] Nakajima, H.; Sano, E.; Ida, M.; Yamahata, S., “80 GHz 4:1 frequency divider IC using nonself-aligned InP/InGaAs heterostructure bipolar transistors,” Electronics Letters, Volume: 36 Issue: 1, pp. 34-35, Jan. 2000.
[38] Pulieta, R.; Mensa, D.; Lee, Q.; Agarwal, B.; Guthrie, J.; Jagannathan, S.; Rodwell, M.J.W., “48 GHz static frequency dividers in transferred-substrate HBT technology,” Electronics Letters, Volume: 34 Issue: 16, pp. 1580-1581, Aug. 1998.
[39] Won-Hyo Lee, Jun-Dong Cho and Sung-Dae Lee, “A High Speed and Low Power Phase-Frequency Detector and Charge-Pump,” IEEE Processing of the ASP-DAC, pp. 269-272, vol.1, 1999.
[40] Mounir Meghelli, Ben Parker, Herschel Ainspan and Mehmet Soyuer, “SiGe BiCMOS 3.3-V Clock and Data Recovery Circuit for 10-Gb/s Serial Transmission System,” IEEE Journal of Solid-State Circuit, Vol. 35, NO. 12, December 2000.
[41] Thomas H. Le and John F. Bulzacchelli, “A 155-MHz Clock Recovery Delay- and Phase-Locked Loop,” IEEE Journal of Solid-State Circuit, Vol. 27, NO. 12, December 1992.
[42] “SONET OC-192 Transport System Generic Criteria,” Bellcore, GR-1377-CORE, Mar. 1998.
[43] Y. Greshishchev and P. Schvan, “SiGe clock an data recovery IC with linear-type PLL for 10-Gb/s SONECT application,” IEEE JSSC, vol. 35, pp.1353-1359, September 2000.
[44] Y. Greshishchev and P. Schvan et al, “A Fully SiGe Receiver IC for 10-Gb/s Data Rate,” IEEE JSSC, vol. 35, pp.1949-1957, Dec. 2000.
[45] L. De Vito, “A versatile clock recovery architecture and monolithic implementation,” in Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design, B. Razavi, Ed. New York, NY:IEEE Press, 1996, pp. 405-42.
[46] Behzad Razavi “Design of Integrated Circuits for Optical Communications,” McGraw-Hill Inc., International Edition, 2003.
[47] M. Meghelli et al., “SiGe BiCMOS 3.3-V Clock and Data Recovery Circuits for 10-Gb/s Serial Transmission System,” IEEE ISSCC, pp. 56-57, 2000.
[48] R. C. Walker et al., “A two-chip 1.5-GBd serial link interface,” IEEE J. Solid State Circuits, vol. 27, pp. 1805-1811, Dec. 1992.
[49] A. Pottbacker, U. Langmann, and H.-U. Schreiber, “ An 8 Gb/s Si Bipolar Phase and Frequency Detector IC for Clock Extraction,” in ISSCC Dig. Tech Paper, Feb. 1992, pp. 162-163.
[50] A. Pottbacker, U. Langmann, and H.-U. Schreiber, “ A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s,” IEEE Journal of Solid-State Circuit, Vol. 27, NO. 12, December 1992.
[51] Shuguang Li, Junyan Ren et al, “ A Clock and Data Recovery Circuit for 2.5Gbps Gigabit Ethernet Transceiver,” IEEE, 2001.
[52] Ahmadreza Rofougaran, Jacob Rael et al, “ A 900MHz CMOS LC-Oscillator with Quadrature Outputs,” IEEE International Solid-State Circuits Conference, 1996.
[53] Ting-Ping Liu, “ A 6.5GHz Monolithic CMOS Voltage-Controlled Oscillator,” IEEE International Solid-State Circuits Conference, 1999.
[54] John W. M. Rogers, Jose A. Macedo, Calvin Plett, “The effect of Varactor Nonlinearity on the Phase Noise of Completely Integrated VCOs,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 9,pp. 1360-1367, September 2000.
[55] L. Lin, L. Tee, and P. R. Gray, “A 1.4-GHz Differential Low-Noise CMOS Frequency Synthesizer Using a Wideband PLL Architecture,” ISSCC Dig. Of Tech. Papers, pp. 204-205, Feb. 2000.
[56] Jun Cao et al, “ OC-192 Transmitter and Receiver in Standard 0.18-μm CMOS,” IEEE Journal of Solid-State Circuit, Vol. 37, NO. 12, December 2002.
指導教授 劉建男、陳巍仁
(Chien-Nan Liu、Wei-Zen Chen)
審核日期 2003-7-9
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡