1.8V 10Gbps 光纖前級接收端電路設計

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姓名

鄭媖蓮(Ying-Lien Cheng) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

1.8V 10Gbps 光纖前級接收端電路設計
(1.8V 10Gbps optical receiver front-end circuits design)

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摘要(中)

隨著網際網路之普及與多媒體資訊傳播時代的來臨¸ 使用者終端對網路骨幹之資料擷取益趨頻繁，同時對頻寬之須求亦日益增加。光纖網路因兼具寬頻與低耗損之特點，為公認寬頻傳輸之最佳介質與未來網際網路之主要骨幹。光通訊系統應用在高速和長程傳輸通訊已經變成一個主要的趨勢，目前資料傳送速度要求為10Gbps的系統包含了電信傳輸(telecommunication OC-192)及資料傳送(data communication 10Gbps Ethernet)等等。此光通訊系統在區域網路的應用上最重要的考量因素之一便是價格，因此，即使已有許多光纖收發機是使用昂貴的GaAs來實現，但由於製程的進步，現在對於以CMOS.18μm來實現光纖收發器也是件相當具有挑戰性的研究。在我的論文中，我們就是利用TSMC .18μm CMOS來完成一個操作在1.8v 10Gbps的 CMOS 光纖前級接收端電路，這包含了轉阻放大器(Transimpedance Amplifier, TIA)及限制放大器(Limiting Amplifier, LA)。在我的論文中已完成了單晶片的設計。
在光纖前級接收端，TIA接受PIN-diode產生的光電流並將它轉為電壓訊號輸出，之後再由LIA將電壓放大到具有固定振幅的輸出訊號。為了提高輸入訊號動態範圍，在TIA中包含了自動增益控制的電路。在1.8V的操作電壓下，轉阻放大器提供一個50dBW和8GHz的-3dB頻寬。至於LIA的設計，我們利用堆疊式對稱式電感來提高頻寬的表現，這種電感的設計比起一般平面不對稱電感的應用上省了50%以上的面積。在1.8V的操作電壓下，限制放大器有5mV的敏感度、8.4GHz的-3dB頻寬和40dB的增益。

摘要(英)

Recently, with the popularity of Internet and multimedia data transportation, the volume of the data transported over the Internet backbone has increased with the growth of the number of Internet users, which has stressed the need for a drastic increase in network bandwidth. Owing to the lowest loss and the highest bandwidth, optical fiber is acknowledged the most appropriate medium for wideband transmission and is a trend for Internet backbone in the future. Optical networking has become a main stream for high speed and long haul data communication. SONET OC-192 is one of the developing high speed communication systems as well as the 10Gbps Ethernet.
One of the most important factors for applying optical system to LAN is its cost. Conventionally, optical transceivers are implemented in expensive GaAs process. Nowadays, with the blooming progress in VLSI technology, several GHz front-end circuits in CMOS process have been successively demonstrated. This thesis explores circuit techniques for optical receiver front-end design in 0.18μm CMOS technology. The objective goals of this research are to realize a single chip of 1.8V 10Gbps optical receiver front-end ICs including a transimpedance amplifier and a limiting amplifier.
In the receiver front-end, the transimpedance amplifier (TIA) receives the photocurrent produced by photodiode and transforms it to voltage output. The limiting amplifier (LIA) further enlarges the tiny voltage to a fixed and sufficiently large output voltage. In order to enhance the input dynamic range, an automatic gain control circuit is included in TIA design. Under 1.8V supply voltage, the TIA provides a conversion gain of 50dBW with a –3dB bandwidth of 8GHz, and its input dynamic range is from –15dBm to 9dBm. The limiting amplifier achieves an input sensitivity of 5mv, -3dB bandwidth of 8.4GHz and conversion gain of 40dB, and the output voltage is fixed at 400mV under 1.8V voltage operation.

關鍵字(中)

★ 轉阻放大器
★ 前級接收端電路
★ 限制放大器

關鍵字(英)

★ transimpedance
★ limiting amplifier
★ receiver front-end circuit

論文目次

Content
Abstract i
Content iii
List of Figures v
List of Table viii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 3
Chapter 2 Receiver Front-End and Passive Component 5
2.1 Introduction 5
2.2 Optical Transceiver Architecture 6
2.3 Specifications of Receiver Front-End 7
2.4 Passive Component 9
2.4.1 Inductor 10
2.4.2 Transformer 11
Chapter 3 Trans-impedance Amplifier 14
3.1 Introduction 14
3.2 Design Considerations 15
3.3 Preamplifier Architecture comparison 16
3.3.1 Architecture Comparison 16
3.3.2 Circuit Topology Comparison 19
3.3.2.1 Common Source Topology 19
3.3.2.2 Common Gate Topology 21
3.4 Transimpedance Amplifier Implementation 22
3.4.1 Trans-impedance Amplifier 24
3.4.1.1 Shunt-Peaking Technique 26
3.4.1.2 Noise Analysis 28
3.4.2 Input Current Generator 29
3.4.3 Automatic Gain Control Circuit Design 30
3.4.3.1 Peak-detector Circuit Design 30
3.4.3.2 Comparator/Integrator/LPF Circuit Design 32
3.4.4 Overall Trans-impedance Amplifier performance 33
Chapter 4 Limiting Amplifier 38
4.1 Introduction 38
4.2 General Considerations 39
4.2.1 Architectures comparison 39
4.2.2 Stage Number Analysis 41
4.2.3 Performance Parameters 45
4.3 CMOS Limiting Amplifier Circuit Design 46
4.3.1 Wide-Band Amplifier 48
4.3.1.1 Cherry-Hooper Architecture 48
4.3.1.2 Bias Current Analysis 51
4.3.1.3 Noise Analysis 56
4.3.2 Offset Cancellation 58
4.3.2.1 Amplifier in feedback path 60
4.3.2.2 Subtractor Circuit Description 60
4.3.3 Output Buffer 61
4.3.4 Overall Limiting Amplifier Performance 63
4.4 Front-End Circuits Design 66
4.4.1 Architecture and Circuit Description 66
4.4.2 Overall Receiver Front-End Performance 68
Chapter 5 Conclusion 71
Bibliography 73

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指導教授

劉建男、陳巍仁
(Chien-Nan Liu、Wei-Zen Chen)

審核日期

2003-7-10

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