| 摘要(英) |
The full of vitality multimedia communications development has increased dramatically 3C industry in the world. Therefore practical applications, tradition ASIC system cannot meet the rapidly and vary development and design integrated. However, standard CPU also cannot meet the rapidly application. Since the system design more complexity and time-to-market pressure, the platform-based design methodology has approached.
In this thesis, we develop a SOPC platform-based design environment for multimedia communications. We adopt the Altera APEX20K200E484-2X device. The JPEG compression is performed on software method in the embedded processor. First, we embed a Nios processor in FPGA (Field Programmable Gate Array). Second, we feed the image data with Nios processor by CMOS sensor. The compressed image data transports to client user by Ethernet daughter board. In this task, we successfully complete the JPEG compression by the Nios processor and web server system. The raw image data is stored in the flash memory. Afterward, the embedded processor can be fetched the raw image data from the flash memory. The compressed image data is stored in SRAM memory. The format of the JPEG image will be transformed to the client by the Ethernet daughter board. Eventually, the user can be accessed the compressed image data through by browser. |
| 參考文獻 |
[1] A. Ferrari and A. Sangiovanni-Vincentelli. System design: Traditional concepts and new paradigms. In Proceedings of International Conference on Computer Design, ICCD ’99, pages 2–12, October 1999.
[2] A. Sangiovanni-Vincentelli. Defining platform-based design. EEdesign, February 2002.
[3] L. P. Carloni, F. De Bernardinis, A. Sangiovanni-Vincentelli, and M. Sgroi. The art and science of integrated systems design. In Proceedings of the 28th European Solid-State Circuits Conference. ESSCIRC 2002. Firenze (Italy), September 2002.
[4] Marco Sgroi, Platform-based Design methodologies for Communication Networks, Engineering - Electrical Engineering and Computer Sciences of the UNIVERSITY OF CALIFORNIA, BERKELEY, Fall 2002.
[5] VSI Alliance, http://www.vsi.org/.
[6] Vasudev Bhaskaran and Konstantions Konstantinides, Image and Video Compression Standards Algorithms and Architectures, Second edition.
[7] Nios Glossary
[8] Nios Embedded Processor – Getting Started User Guide, http://www.altera.com/literature/ug/ug_nios_gsg_apex_20k20e.pdf.
[9] SOPC Builder Datasheet, http://www.altera.com/literature/ds/ds_sopc.pdf.
[10] Nios Embedded Processor Development Board datasheet, http://www.altera.com/literature/ds/ds_nios_board_apex_20k200e.pdf.
[11] Nios Development Board Schematic
[12] Simulating Nios Embedded Processor Designs, http://www.altera.com/literature/an/an189.pdf.
[13] Avalon Bus Specification – Reference Manual, http://www.altera.com/literature/manual/mnl_avalon_bus.pdf.
[14] Simultaneous Multi-Mastering with the Avalon Bus, http://www.altera.com/literature/an/an184.pdf.
[15] Nios Ethernet – Development Kit User Guide, http://www.altera.com/literature/ug/ug_niosedk.pdf.
[16] Nios UART Data Sheet, http://www.altera.com/literature/ds/ds_nios_uart.pdf.
[17] Nios DMA Data Sheet, http://www.altera.com/literature/ds/ds_nios_dma.pdf.
[18] Nios PIO Data Sheet, http://www.altera.com/literature/ds/ds_nios_pio.pdf.
[19] Nios SPI Data Sheet, http://www.altera.com/literature/ds/ds_nios_spi.pdf.
[20] Nios Timer Data Sheet, http://www.altera.com/literature/ds/ds_nios_timer.pdf.
[21] Nios2.1 CPU Datasheet, http://www.altera.com/literature/ds/ds_nioscpu.pdf.
[22] Custom Instructions for the Nios Embedded Processor, http://www.altera.com/literature/tt/tt_nios_ci.pdf.
[23] Nios Embedded Processor – Software Development Reference Manual, http://www.altera.com/literature/manual/mnl_niossft.pdf.
[24] Nios Embedded Processor – 16-Bit Programmer’s Reference Manual, http://www.altera.com/literature/manual/mnl_nios_programmers16.pdf.
[25] Nios Embedded Processor – 32-Bit Programmer’s Reference Manual, http://www.altera.com/literature/manual/mnl_nios_programmers32.pdf.
[26] GNUPro Toolkit – User's Guide for Altera Nios, http://www.altera.com/literature/third-party/nios_gnupro.pdf.
[27] Nios Software Development Tutorial, http://www.altera.com/literature/tt/tt_nios_sw.pdf.
[28] Nios Hardware Development Tutorial, http://www.altera.com/literature/tt/tt_nios_hw.pdf.
[29] Using SOPC Builder with Excalibur Devices Tutorial, http://www.altera.com/literature/tt/tt_sopc_exdev.pdf.
[30] Nios Tutorial (APEX Device), http://www.altera.com/literature/tt/tt_nios_hw_apex_20k200e.pdf.
[31] Plugs Ethernet Library Reference Manual, http://www.altera.com/literature/manual/mnl_plugs.pdf.
[32] MasterBlaster Serial/USB Communications Cable Data Sheet, http://www.altera.com/literature/ds/dsmaster.pdf.
[33] ByteBlasterMV Parallel Port Download Cable Data Sheets, http://www.altera.com/literature/ds/dsbytemv.pdf.
[34] AN225: LeonardoSpectrum & Quartus II Design Methodology, http://www.altera.com/literature/an/an225.pdf.
[35] AN161: Using the LogicLock Methodology in the Quartus II Design Software, http://www.altera.com/literature/an/an161.pdf.
[36] Quartus II Installation & Licensing for PCs Manual, http://www.altera.com/literature/manual/quartus_install.pdf.
[37] Ming-Chich Chen, and Ing-Jer Huang, A MAC IP and Its Development, Dept. of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan.
[38] IEEE Std. 802.3, 2000 edition. |
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