類神經網路應用於高階功率模型之研究

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姓名

薛文燦(Wen-Tsan Hsieh) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

類神經網路應用於高階功率模型之研究
(A Novel High-Level Power Model Using Neural Network)

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摘要(中)

在預估複雜數位電路的功率消耗時，常用功率模型的方式來預估，這個方法因為在使用上不需要詳細電路的內部資訊，所以在非常高的設計層次中，便能預估到電路的功率消耗。而在這方面目前大多數都是以查表法來實現。然而，當我們利用這種查表法的方式來建立大電路的功率模型時，很有可能為了達到高準確度的目的而將表格大小呈指數比例成長，而且在記錄整個表格的時候，常因為很難去控制輸出轉態機率而造成無法預期的製表時間，這都是我們不願見到的。
在這篇論文中，我們著力研究在利用類神經網路來建立一種嶄新的功率消耗模型，利用類神經網路來學習輸入資訊及相對應功率消耗的值，進而應用在高階功率估測上。我們的類神經功率模組擁有相當低的網路複雜度，不像查表法一樣會與電路大小呈指數性成長，透過特徵萃取處理程序後，我們的模組並不會與電路大小有那麼直接的關係，且因為類神經網路的特性，使得這個簡單的模型還可以擁有很好的準確度。在特徵萃取處理程序中，相較於查表法，我們的是非常簡單且直觀的。更重要的是，這種類神經功率消耗模型不需要內部的電路資訊，不僅保護了智慧財產權，更適合於將來IP盛行的時代。從我們的實驗數據裡可看出，在廣泛的輸入變化範圍內，此功率模型依然保有相當的準確度，足見此模型之效能確實符合需求。

摘要(英)

For complex digital circuits, building their power models is a popular approach to estimate their power consumption without detailed circuit information. In the literature, most of power models are built with lookup tables. However, building the power models with lookup tables may become infeasible for large circuits because the table size would increase exponentially to meet the accuracy requirement. Furthermore, because it is hard to control the distribution of average output transition density, those approaches suffer problems with unpredicted characterization time to fill the lookup tables.
In this thesis, we propose a novel power modeling approach for complex circuits by using neural networks to learn the relationship between power dissipation and input/output characteristic vector during simulation. Our neural power model has very low complexity such that this power model can be used for complex circuits. Using such a simple structure, the neural power models can still have high accuracy because they can automatically consider the non-linear power distributions. Unlike the power characterization process in traditional approaches, our characterization process is very simple and straightforward. More importantly, using the neural power model for power estimation does not require any transistor-level or gate-level description of the circuits, which is very suitable for IP protection. The experimental results have shown that the estimations are accurate and efficient for different test sequences with wide range of input distributions.

關鍵字(中)

★ 類神經網路
★ 功率預估
★ 高階功率模型

關鍵字(英)

★ high level power estimation
★ neural network
★ power model

論文目次

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 5
Chapter 2 Related Works 6
2.1 Introduction 6
2.2 Power Consumption of CMOS Digital Circuits 7
2.3 Overview of Power Estimation Techniques 8
2.4 High-Level Power Estimation 10
2.5 Traditional Table-Based Power Model 11
2.6 Summary 13
Chapter 3 Artificial Neural Network 14
3.1 Introduction 14
3.2 Biological Neurons VS. Artificial Neurons 15
3.3 Feed-Forward Neural Network 17
3.4 Operations of Neural Network 18
3.5 Training Algorithms 19
3.6 The Properties of Neural Network 21
3.7 Summary 23
Chapter 4 Power Modeling with Neural Network 25
4.1 Introduction 25
4.2 Parameters of Neural Network 26
4.3 Training Process for the Neural Network 28
4.4 Power Estimation with the Neural Model 30
4.5 Implementation and Experimental Results 31
4.6 Discussion 33
4.7 Summary 35
Chapter 5 Improved Neural Power Model 36
5.1 Introduction 36
5.2 Another Characterization Process 36
5.3 Comparison 38
5.4 Implementation and Experimental Results 39
5.5 Summary 41
Chapter 6 Conclusions 42
Reference 43

參考文獻

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指導教授

劉建男(Chien-Nan Liu)

審核日期

2003-7-15

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