|| I. Martinez, P. Delatte and D. Flandre, “Characterization, simulation and modeling of PLL under irradiation using HDL-A,” Proceedings of the IEEE/ACM International Workshop on Behavioral Modeling and Simulation, Oct. 2000, Page(s): 57 –61|
 K.W. Current, J.F. Parker and W.J. Hardaker, “On behavioral modeling of analog and mixed-signal circuits,” Signals, Systems and Computers, 1994. 1994 Conference Record of the Twenty-Eighth Asilomar Conference on , Volume: 1 , 31 Oct.-2 Nov. 1994 Page(s): 264 -268 vol.1
 F. Herzel and B. Razavi, “A study of oscillator jitter due to supply and substrate noise ,”Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on] , Volume: 46 , Issue: 1 , Jan. 1999 Pages:56 - 62
 T. Murayama and Y. Gendai ,“A top-down mixed-signal design methodology using a mixed-signal simulator and analog HDL,” Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European , 16-20 Sept. 1996 Pages:59 - 64
 B. De Smedt and G..Gielen , “Models for Systematic Design and Verification of Frequency Synthesizers,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on] , Volume: 46 , Issue: 10 , Oct. 1999 Pages:1301 - 1308
 A. Demir, E. Liu, A.L. Sangiovanni-Vincentelli, and I. Vassiliou, “Behavioral simulation techniques for phase/delay-locked systems ,” Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994 , 1-4 May 1994
Pages:453 - 456
 OVI Verilog-A Language Reference Manual Revision Version 2.0, Jan.2000.
 AffirmaTM Verilog-A Language Reference, Product Version 4.4.6, Cadence Design Systems,Inc.
 CIC訓練課程 Verilog-A Training Manual, 國家晶片系統設計中心, February 2002.
 CIC訓練課程 Mixed-Signal IC Design Kit Training Manual, 國家晶片系統設計中心, Feb. 2002.
 I. Miller and T. Cassagnes, “Verilog-A and Verilog-AMS provides a new dimension in modeling and simulation,” Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems, March 2000, Page(s): C49/1 -C49/6
 Behzad Razavi, Design of Analog CMOS Integrated Circuits, Chapter 15 “Phase-Locked Loops”.
 黃清吉, “以回填法建立鎖相迴路之行為模型的研究,” 國立中央大學電機工程研究所碩士論文, June 2003.
 Jie Sun, M. Li and J. Wilstrup, “A demonstration of deterministic jitter (DJ) deconvolution,” Instrumentation and Measurement Technology Conference, 2002. IMTC/2002. Proceedings of the 19th IEEE , Volume: 1 , 21-23 May 2002 Pages:293 - 298 vol.1
 P. Acco, M.P. Kennedy, C. Mira, B. Morley and B. Frigyik, “Behavioral modeling of charge pump phase locked loops,” Proceedings of the ISCAS on Circuits and Systems, vol.1, June 1999, Page(s): 375 –378.
 A. Yufera and A. Rueda, “Studying the effects of mismatching and clock-feedthrough in switched-current filters using behavioral simulation,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal, vol.44, iss.12, Dec. 1997, Page(s): 1058 –1067.
 A. Fakhfakh, N. Milet-Lewis, J. Tomas and H. Levi, “Behavioural Modelling of phase noise and jitter in VCO with VHDL-AMS,” Circuits and Systems for Communications, 2002. Proceedings. ICCSC '02. 1st IEEE International Conference on , 26-28 June 2002 Pages:370 - 373
 M. Takahashi, K.Ogawa and K.S. Kundert, “VCO jitter simulation and its comparison with measurement,” Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific , 18-21 Jan. 1999
Pages:85 - 88 vol.1
 K.kundert, “Modeling and simulation of jitter in PLL frequency synthesizers,” white paper of Cadence Design System ,inc, 2001