|| C. Berrou, A. Glavieux, and P. Thitimajshima, “Near Shannon limit error-correcting coding and decoding: Turbo Codes,” in Proc. IEEE Int. Conf. Communications, 1993, pp. 1064-1070.|
 J. Hagennauer and L. Papke, “Decoding ‘turbo’-codes with the soft output Viterbi algorithm (SOVA),” in Proc. IEEE Int. Symp. Information Theory, 1994, p.164.
 P. Robertson, E. Villebrun, P. Hoeher, “A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain,” in Proc. IEEE Int. Conf. Communications, 1995, pp. 1009-1013.
 B. Sklar, “A primer on turbo codes concepts,” IEEE Communications Mag., pp. 94-102, Dec. 1997.
 A. J. Viterbi, “An intuitive justification and simplified implementation of the MAP decoder for convolutional codes,” IEEE J. Selected Area in Communications, vol. 16, pp. 260-264, Feb. 1998.
 E. Boutillon, W. J. Gross, and P. G. Gulak, “VLSI architectures for the MAP algorithm,” IEEE Trans. Communications, vol. 51, pp. 175-185, Feb. 2003.
 T. A. Summers and S. G. Wilson, “SNR mismatch and online estimation in turbo decoding,” IEEE Trans. Communications, vol. 46, pp. 421 –423, April 1998.
 “Technical specification group radio access network; multiplexing and channel coding (FDD),” 3rd Generation Partnership Project, 3GPP TS25.212 v5.1.0, 2002.
 “Physical layer standard for cdma2000 spread spectrum systems,” 3rd Generation Partnership Project2, 3GPP2 C.S0002-C, v1.0, 2002.
 M. A. Bickerstaff, D. Garrett, T. Prokop, C. Thomas, B. Widdup, Gongyu Zhou, L. M. Davis, G. Woodward, G. Nicol, and Ran-Hong Yan, “A unified turbo/viterbi channel decoder for 3GPP mobile wireless in 0.18-/spl mu/m CMOS,” IEEE J. Solid-State Circuits, vol. 37, pp. 1555-1564, Nov 2002.
 S. Agarwala, T. Anderson, A. Hill, M. D. Ales, R. Damodaran, P. Wiley, S. Mullinnix, J. Leach, A. Lell, M. Gill, A. Rajagopal, A. Chachad, M. Agarwala, J. Apostol, M. Krishnan, Duc Bui, Quang An, N. S. Nagaraj, T. Wolf, T. T. Elappuparackal, “A 600-MHz VLIW DSP,” IEEE J. Solid-State Circuits, vol. 37, pp.1532-1544, Nov. 2002.
 S. Benedetto and G. Montorsi, “Unveiling turbo-codes: some results on parallel concatenated coding schemes,” IEEE Trans. Information Theory, vol. 42, pp. 408-428, Mar. 1996.
 D. Cress, W. Ebel, “ Turbo code implementation issues for low latency, low power applications,” in Proc. Virginia Tech’s Eighth Symp. Wireless Personal Communications, 1998, pp.191-200.
 S. Halter, M. Oberg, P. M. Chau, P. H. Siegel, “Reconfigurable signal processor for channel coding and decoding in low power SNR wireless communications,” in Proc. IEEE Workshop on Signal Processing System, 1998, pp. 260-274.
 S. Hong, J. Yi, W.E. Stark, “VLSI design and implementation of low complexity adaptive turbo-code encoder and decoder for wireless mobile communication applications,” in Proc. IEEE Workshop on Signal Processing System, 1998, pp. 233-242.
 C. Berrou, P. Combells, P. Penard, B. Talibart, “An IC for turbo-codes encoding and decoding,” in Proc. IEEE Int. Solid-State Circuit Conf., 1995, pp. 90-91.
 D, Garrett, M. Stan, “Low power Architecture of the soft output Viterbi Algorithm,” in Proc. Int. Symp. Low Power Electronics and Design, 1998, pp. 262-167.
 L. Lin, C.Y. Tsui, R. S. Cheng, “Low power soft output Viterbi decoder scheme for turbo code decoding,” in Proc. IEEE Int. Symp. Circuit and Systems, 1997, pp. 1369-1372.
 E. Luthi, E. Casseau, “High rate soft output Viterbi decoder,” in Proc. European Design and Test Conf., 1996, pp. 130-132.
 J. Hagennauer, E. Ofeer, and L. Papke, “Iterative decoding of binary block and convolutional code,” in Proc. IEEE Int. Symp. Information Theory, 1996, pp. 429-445.
 J. P. Woodard, and L. Hanzo, “Comparative study of turbo decoding techniques: an overview,” IEEE Trans. Vehicular Technology, vol. 49, pp. 2208 –2233, Nov. 2000.
 L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, “Optimal decoding of linear codes for minimizing symbol error rate,” IEEE Trans. Information Theory, vol. IT-20, pp. 284-287, Mar. 1974.
 J. A. Erfanian and S. Pasupathy, “Low-complexity parallel-structure symbol-by-symbol detection for ISI channels,” in Proc. IEEE Pacific Rim Conf. Communications, Computers and Signal Processing, 1989, pp.350-353.
 C. schurgers, F. Chatthoor, and M. Engels, “Memory optimization of MAP turbo decoder algorithms,” IEEE Trans. VLSI Systems, vol. 9, pp. 305-312, Apr. 2001.
 H. Dawid, and H. Meyr, “Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding,” in Proc. IEEE Int. Symp. Personal, Indoor and Mobile Radio Communications, 1995, pp.193-197.
 S. S. Piterson and S. A. Barbulescu, “A simplification of modified Bahl decoding algorithm for systematic convolutional codes,” in Proc. Int. Symp. Information Theory and Its Applications, 1994, pp.1073-1077.
 H. Dawid, G. Gehnen, and H. Meyr, “MAP channel decoding: Algorithm and VLSI architecture,” in Proc. IEEE Workshop on VLSI Signal Processing, 1994, pp.141-143.
 A. Raghupathy, and K. J. R. Liu, “A transformation for computational latency reduction in turbo-MAP decoding,“ in Proc. IEEE Int. Symp. Circuit and Systems, 1999, pp. 402 –405.
 R. Y. Shao, S. Lin, and M.P. C. Fossorier, “Two simple stopping criteria for turbo decoding,” IEEE Trans. Communications, vol. 47, pp. 1117–1120, Aug. 1999.
 A. Matache , et-al, “Stopping Rules for Turbo decoders,” JP: TMO Progress Report, 42-142, Aug. 15, 2000.
 K. R. Narayanan and G. L. stuber, “A Novel ARQ technique using the turbo coding principle,” IEEE Trans. Communications letters, vol. 1, pp. 49–51, Mar. 1997.
 F. Gilbert, A. Worm, and N. Wehn, “Low-power implementation of a turbo-decoder on programmable architectures,” in Proc. Asia and South Pacific Design Automation Conf., 2001, pp. 400–403.
 Myoung-Cheol Shin, In-Cheol Park, “A programmable turbo decoder for multiple 3G wireless standards,” in Proc. IEEE Int. Solid-State Circuit Conf., 2003, pp. 1-10.
 M. Bickerstaff, L. Davis, C. Thomas, D. Garrett, C. Nicol, “A 24 Mb/s Radix-4 LogMAP Turbo Decoder for 3GPP-HSDPA Mobile Wireless,” in Proc. IEEE Int. Solid-State Circuit Conf., 2003, pp. 1-10.
 Kai Huang, Fan-Min Li, Pei-Ling Shen, and An-Yeu Wu, “VLSI design of dual-mode Viterbi/Turbo decoder for 3GPP,” in Proc. IEEE Int. Symp. Circuit and Systems, 2004, pp. 773 –776.