適用於二維及三維半導體元件模擬的可調變式元件切割法

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姓名

鄭義憲(Yi-Shian Jeng) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用於二維及三維半導體元件模擬的可調變式元件切割法
(Flexible Device Partition Method in 2-D and 3-D Semiconductor Device Simulation)

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摘要(中)

本論文主要是探討如何有效的節省在模擬半導體元件時所需要的記憶體空間，利用元件分割法可以在執行程式時大大的減少所需要的記憶體空間。因此，我們可以藉此優點來增加元件的點數而得到更精確的模擬結果。利用所開發的可調變式元件分割法，我們可以根據當時所需要的狀況來自由的調整欲分割的數目，使得模擬的過程能更加有效率，並將之應用在二維及三維的半導體元件模擬上。最後，我們將會利用上述的方法去模擬傳輸閘，並利用其模擬的結果來說明傳輸閘運用在電路設計上的優點。

摘要(英)

In this thesis, we focus on how to effectively save the required memory space when simulate a semiconductor device. We can substantially reduce the required memory space by using device partition method. So, we can increase the node numbers by taking the advantage of device partition method and get the most accurate result. We developed the Flexible Device Partition Method. By using this method, we can partition the device into several parts as we want. So it can work more efficiently, and we will apply it to 2-D and 3-D device simulation. Finally, we will use this method to simulate a transmission-gate circuit and show the advantage of T-G in circuit design.

關鍵字(中)

★ 元件切割法

關鍵字(英)

★ Device Partition Method

論文目次

Contents
1. Introduction………………………………………………………………………………...…………………1
2. Flexible Partition Method…………………………………………….…..……………….......3
2.1 Introduction…………………………………………………………………………………………………..3
2.2 Boundary Condition Between Two Parts…………...………………………………………....5
2.2.1 Boundary Condition in 2-D…………...………………………………………………..…….6
2.2.2 Boundary Condition in 3-D…………...………………………………..…………………….8
2.3 Buffer’s Purpose…………………………………………………………………...……………………….9
2.4 Solver for Matrix Equation………………………………………………………………..………..12
2.4.1 Band Solver…………………………………………………………………………….…………..12
2.4.2 Levelized Incomplete LU Solver………………………………………….…………….14
3. Simulation Result and Discussion………………………………………...…….....17
3.1 2-D p-n Diode Simulation…………………………………………..………………………………17
3.2 2-D MOSFET Device simulation……………………………………………………………….20
3.3 3-D MOSFET Device simulation……………………………………………………………….23
4. Application of FDPM in 2-D multi-transistor simulation
………………………………………………………………………………………………………………………………...26
4.1 CMOS Inverter…………………………………………………………………………………...………..26
4.2 Transmission Gate….…………………………………………………………….………………………29
4.3 Click at the Input…….……………………………………………………..………………..……............31
4.3.1 Only N-type MOS transistor and Only P-type MOS transistor……………….32
4.3.2 Combining the NMOS and PMOS transistors in parallel…………….………….34
4.4 Click at the Gate…….………………………………………………………..………..………………….36
5. Conclusion……………………………………………………………………………………………………38

參考文獻

Reference
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California Berkeley, ERL Memo ERL-M520, May 1975.
[5] K. Mararam and D. O. Pederson, “Coupling algorithms for mixed-level circuit and device simulation”, IEEE transactions on computer-aided design, vol. 11, no.8, pp. 1003-1010, 1992.
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[9] S. Selberherr, “Analysis and simulation of semiconductor device”, New York: Springer, 1984.
[10] A. A. Abou-Auf, “Stochastic worst-case test vector for CMOS circuits exposed to total dose”, GOMAC, 1997, pp.89-92

指導教授

蔡曜聰(Yao-Tsung Tsai)

審核日期

2004-7-8

推文