博碩士論文 91521035 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:6 、訪客IP:3.237.67.179
姓名 鄭義憲(Yi-Shian Jeng)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 適用於二維及三維半導體元件模擬的可調變式元件切割法
(Flexible Device Partition Method in 2-D and 3-D Semiconductor Device Simulation)
相關論文
★ 表面電漿共振效應於光奈米元件之數值研究★ 金氧半電容元件的暫態模擬之數值量測
★ 雙載子電晶體在一維和二維空間上模擬的比較★ 改善後的階層化不完全LU法及其在二維半導體元件模擬上的應用
★ 一維雙載子接面電晶體數值模擬之驗證及其在元件與電路混階模擬之應用★ 階層化不完全LU法及其在準靜態金氧半場效電晶體電容模擬上的應用
★ 探討分離式簡化電路模型在半導體元件模擬上的效益★ 撞擊游離的等效電路模型與其在半導體元件模擬上之應用
★ 二維半導體元件模擬的電流和電場分析★ 三維半導體元件模擬器之開發及SOI MOSFET特性分析
★ 元件分割法及其在二維互補式金氧半導體元件之模擬★ 含改良型L-ILU解法器及PDM電路表述之二維及三維元件數值模擬器之開發
★ 含費米積分之高效率載子解析模型及其在元件模擬上的應用★ 量子力學等效電路模型之建立及其對元件模擬之探討
★ 整合式的混階模擬器之開發及其在振盪電路上的應用★ 用時域模擬法探討S參數及其應用
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 本論文主要是探討如何有效的節省在模擬半導體元件時所需要的記憶體空間,利用元件分割法可以在執行程式時大大的減少所需要的記憶體空間。因此,我們可以藉此優點來增加元件的點數而得到更精確的模擬結果。利用所開發的可調變式元件分割法,我們可以根據當時所需要的狀況來自由的調整欲分割的數目,使得模擬的過程能更加有效率,並將之應用在二維及三維的半導體元件模擬上。最後,我們將會利用上述的方法去模擬傳輸閘,並利用其模擬的結果來說明傳輸閘運用在電路設計上的優點。
摘要(英) In this thesis, we focus on how to effectively save the required memory space when simulate a semiconductor device. We can substantially reduce the required memory space by using device partition method. So, we can increase the node numbers by taking the advantage of device partition method and get the most accurate result. We developed the Flexible Device Partition Method. By using this method, we can partition the device into several parts as we want. So it can work more efficiently, and we will apply it to 2-D and 3-D device simulation. Finally, we will use this method to simulate a transmission-gate circuit and show the advantage of T-G in circuit design.
關鍵字(中) ★ 元件切割法 關鍵字(英) ★ Device Partition Method
論文目次 Contents
1. Introduction………………………………………………………………………………...…………………1
2. Flexible Partition Method…………………………………………….…..……………….......3
2.1 Introduction…………………………………………………………………………………………………..3
2.2 Boundary Condition Between Two Parts…………...………………………………………....5
2.2.1 Boundary Condition in 2-D…………...………………………………………………..…….6
2.2.2 Boundary Condition in 3-D…………...………………………………..…………………….8
2.3 Buffer’s Purpose…………………………………………………………………...……………………….9
2.4 Solver for Matrix Equation………………………………………………………………..………..12
2.4.1 Band Solver…………………………………………………………………………….…………..12
2.4.2 Levelized Incomplete LU Solver………………………………………….…………….14
3. Simulation Result and Discussion………………………………………...…….....17
3.1 2-D p-n Diode Simulation…………………………………………..………………………………17
3.2 2-D MOSFET Device simulation……………………………………………………………….20
3.3 3-D MOSFET Device simulation……………………………………………………………….23
4. Application of FDPM in 2-D multi-transistor simulation
………………………………………………………………………………………………………………………………...26
4.1 CMOS Inverter…………………………………………………………………………………...………..26
4.2 Transmission Gate….…………………………………………………………….………………………29
4.3 Click at the Input…….……………………………………………………..………………..……............31
4.3.1 Only N-type MOS transistor and Only P-type MOS transistor……………….32
4.3.2 Combining the NMOS and PMOS transistors in parallel…………….………….34
4.4 Click at the Gate…….………………………………………………………..………..………………….36
5. Conclusion……………………………………………………………………………………………………38
參考文獻 Reference
[1] A. R., Brown, A. Asenov, S. Roy and J. R. Barker, “Development of a parallel 3D finite element power semiconductor device simulator”, IEE Colloquium, Physical Modeling of Semiconductor Devices, 1995.
[2] D. A., Neamen, “Electronic Circuit Analysis and Design”, The McGraw-Hill Companies, Inc., 1996.
[3] A. S. Sedra and Kenneth C. Smith, “Microelectronic Circuit”, Oxford University Press, Inc., 1998.
[4] L. W. Nagel, “SPICE2:A computer to simulate semiconductor circuit”, Univ.
California Berkeley, ERL Memo ERL-M520, May 1975.
[5] K. Mararam and D. O. Pederson, “Coupling algorithms for mixed-level circuit and device simulation”, IEEE transactions on computer-aided design, vol. 11, no.8, pp. 1003-1010, 1992.
[6] J. W. Lee, “An equivalent circuit approach to mixed-level device and circuit simulation”, M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, Jun. 1997.
[7] C. C. Chang, C. H. Huang, J. F. Dai, S. J. Li, and Y. T. Tsai, “ 3-D numerical device simulation including equivalent-circuit model”, in IEDMS 2002, p.542-544
[8] Y. T. Tsai, C. Y. Lee, and M. K. Tsai, “Levelized incomplete LU method and its application to semiconductor device simulation”, Solid-State Electronics, vol. 44, pp. 1069-1075, 2000.
[9] S. Selberherr, “Analysis and simulation of semiconductor device”, New York: Springer, 1984.
[10] A. A. Abou-Auf, “Stochastic worst-case test vector for CMOS circuits exposed to total dose”, GOMAC, 1997, pp.89-92
指導教授 蔡曜聰(Yao-Tsung Tsai) 審核日期 2004-7-8
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明