博碩士論文 91521036 詳細資訊




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姓名 蔡文洲(Wen-Chou Tsai)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 矽鍺異質源/汲極結構與pn二極體之研製
(Study and Processing of Hetero-SiGe/Si S/D Structure and P-N Diode)
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摘要(中) 摘要
在本論文中,利用ICP與smart-EPDTM製作出超淺接面源/汲極結構,並且搭配高溫濕氧化(wet oxidation)將受損的表面氧化後,由氫氟酸水溶液將氧化後的缺陷層移除,完成淺接面源/汲極結構的製作。
本論文的另一重點為異質矽鍺/矽pn二極體的製作。利用LPCVD成長複晶矽鍺材料並以黃光設備搭配電漿蝕刻回蝕刻技術將pn二極體圖形定義出來,完成製作嵌入式/提升式異質矽鍺/矽pn二極體。而在元件直流特性上,嵌入式異質矽鍺/矽pn二極體無論是在開啟電壓(Von)、理想因數(n)、逆向飽和電流(Isat)與崩潰電壓(Vbd)有較佳的特性表現,同時也展現此異質結構較不易受鍺含量多寡的限制以及有效的抑制短通道效應,具實現高速與低功率消耗的元件設計之潛能。
運用嵌入式異質矽鍺/矽結構於MOSFETs的源/汲極上將可壓縮短通道效應,實現未來奈米金氧半電晶體發展之趨勢。因此,嵌入式矽鍺源極/汲極結構的確是一個適合運用於尺寸小、速度快與消耗功率低的奈米電子元件。
摘要(英) Abstract
In this thesis, we fabricated shallow junction S/D structure by ICP and smart-EPDTM. We applied high temperature wet oxidation to oxidize the defective surface. The oxidized defective layer was then removed by hydrofluoric (HF) acid.
We also fabricated hetero-SiGe/Si P-N diode. We first grew poly-SiGe material by LPCVD. The recessed/raised P-N diode was then patterned by yellow light equipments and plasma-etching-back techniques. As for DC characteristics, the recessed P-N diode performs better in turn on voltage (Von), ideality factor (n), reverse saturation current (Isat), junction capacitance (Cj), and breakdown voltage (Vbd). We also show that the recessed heterostructure is less dependent on the Ge content and effectively suppresses short-channel-effect. Therefore, the recessed hetero-SiGe/Si P-N diode is one of the best candidates to realize high speed and low power consumption.
By incorporating recessed hetero-SiGe/Si structure into the S/D of MOSFETs, we can compress short-channel-effect, and thus continue the scaling trend of MOSFETs into the nano-scale region. Therefore, recessed SiGe/Si S/D structure can realize nano-scale electronic devices with high speed and low power consumption.
關鍵字(中) ★ 超淺接面源/汲極結構
★ 高溫濕氧化
★ 異質矽鍺/矽pn二極體
★ 嵌入式/提升式異質矽鍺/矽pn二極體
★ 開啟電壓
★ 理想因數
★ 逆向飽和電流
★ 崩潰電壓
★ 金氧半電晶體
關鍵字(英) ★ shallow junction S/D structure
★ turn on voltage
★ ideality factor
★ reverse saturation current
★ junction capacitance
★ breakdown voltage
★ short-channel-effect
★ wet oxidation
★ hetero-SiGe/Si P-N diode
★ recessed/raised P-N diode
論文目次 目錄
摘要…………………………………………….……………………….Ⅰ
致謝……………………………………………………………………..Ⅱ
圖目錄…………………………………………………………………..Ⅲ
表目錄…………………………………………………………………..Ⅸ
序章 論文結構介紹…………………………………………………..Ⅹ
第一章 介紹……………………………………………………………..1
1-1 前言…………………………………………………………….1
1-2 研究動機……………………………………………………….1
1-3 研究目的與應用……………………………………………….5
第二章 矽鍺異質結構在金氧半電晶體之可能應用…………………13
2-1 前言…………………………………………………………...13
2-2 異質接面矽鍺/矽材料特性之簡述…………………………..14
2-3 矽鍺源/汲極結構之應用……………………………………..15
2-4 異質矽鍺源/汲極之可能形成方法與比較…………………..16
2-4-1 鍺離子佈植源/汲極結構………………………………..17
2-4-2 提升式矽鍺源/汲極結構………………………………..18
2-4-3 嵌入式矽鍺源/汲極結構………………………………..18
2-4-3.1 結構設計…………………………………………19
2-4-3.2 模擬結果與分析…………………………………19
2-5 結論…………………………………………………………...21
第三章 嵌入式異質矽鍺源/汲極結構之關鍵製程開發……………...35
3-1 前言…………………………………………………………...35
3-2 超淺接面源/汲極製程步驟…………………………………..35
3-2-1 乾式電漿蝕刻製程設備………………………………...36
3-2-1.1 蝕刻反應器………………………………………37
3-2-1.2 製程監督和終點偵測……………………………38
3-2-2 複晶矽閘極蝕刻………………………………………...39
3-2-3 間隙壁回蝕刻…………………………………………...43
3-2-4 源/汲極等向性蝕刻……………………………………..49
3-3 複晶矽鍺薄膜的成長……………………………….………..51
3-4 結論…………………………………………………………...52
第四章 異質矽鍺/矽pn二極體製程與量測分析……………………..71
4-1 前言…………………………………………………………...71
4-2 矽鍺/矽pn二極體製程步驟………………………………….71
4-3 pn接面二極體的電性特性…………………………………...73
4-4 電性量測……………………………………………………...76
4-4-1 邊際效應………………………………………………...77
4-4-2 順向偏壓與電流特性…………………………………...78
4-4-2.1 開啟電壓…………………………………………78
4-4-2.2 理想因數…………………………………………79
4-4-3逆向偏壓與電流特性…………………………………….80
4-4-3.1逆向飽和電流……………………………………..80
4-4-3.2崩潰電壓…………………………………………..81
4-4-3.3接面電容…………………………………………..83
4-5 結論…………………………………………………………...83
第五章 總結與未來展望……………………………………………....99
參考文獻資料…………………………………………………………101
參考文獻 參考文獻資料
[1] G. W. Taylor, “Subthreshold conduction in MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-25, pp. 337, 1978.
[2] R. R. Troutman, “VLSI limitations from drain-induced barrier lowering,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 383, 1979.
[3] 林鴻志,“奈米金氧半電晶體元件技術發展趨勢(I)”,毫微米通訊,七卷一期,pp. 1-12,2001。
[4] J. H. Stathis, “Reliability projection for ultra-thin oxides at low voltage,” IEDM Tech. Digest, pp. 167, 1998.
[5] YAN. R. H., OURMAZD, A., and LEE, K. F., ”From bulk to SOI to bulk,” IEEE Trans. ED-39, pp. 1704-1710, 1992.
[6] J. Y. Tsai et al, “DIBL considerations of extended drain structure for 0.1 μm MOSFET's,” IEEE Electron Device Lett., EDL-17, pp. 331, 1996.
[7] Y. Taur et al., “25 nm CMOS design considerations,” IEDM Tech. Digest, pp. 789, 1998.
[8] P. W. Li, Y. F. Yang, E. S. Yang, J. Chu, and B. S. Meyerson, “SiGe pMOSFETs with gate oxide fabrication by microwave electron cyclotron resonance plasma,” IEEE Electron Device Lett., vol. 45, pp. 402, 1994.
[9] Y. C. Yeo et al., “Enhanced Performance in Sub-100nm CMOSFETs using Strained Epitaxial Silicon-Germanium,” IEDM, pp. 753, 2000.
[10] 石靖節,“應變型矽鍺通道金氧半電晶體之研究”,碩士論文,國立中央大學,民國92年。
[11] V. E. Houtsma et al., “Stress-induced leakage current in p+ poly MOS capacitors with poly-Si and poly-Si0.7Ge0.3 gate material,” IEEE Electron Device Lett., EDL-20, pp. 314, 1999.
[12] Y. V. Ponomarev et al., “Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 μm CMOS technology,” IEDM Tech. Digest, pp. 829, 1997.
[13] T. –J. King et al., “A polycrystalline-Si1-xGex-gate CMOS technology,” Proc. IEDM, pp.253, 1990.
[14] T. –J. King et al., “ Electrical properties of heavily doped polycrystalline silicon-germanium films,” IEEE Tran. Electron Devices, ED-41, pp. 228, 1994.
[15] R. People and J. C. Bean, “Band alignments of coherently strained GexSi1-x/Si heterostructures on <001> GeySi1-y substrates,” Appl. Phys. Lett., vol. 48, pp. 538, 1986.
[16] G. W. Taylor, “Subthreshold conduction in MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-25, pp. 337, 1978.
[17] R. R. Troutman, “VLSI limitations from drain-induced barrier lowering,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 383, 1979.
[18] R. People, “Indirect band gap of coherently strained GexSi1-x bulk alloys on <001> silicon substrates,” Phys. Rev., vol. B32, pp. 1405, 1985.
[19] T. J. King et al., “A low-temperature (⩽ 500°C) silicon-germanium MOS thin-film transistor technology for large-area electronics,” Proc. IEDM, pp. 567, 1991.
[20] “Electrical measurement of the bandgap of N+ and P+ SiGe formed by Ge ion implantation,” in Mater. Res. Symp. Proc., vol. 500, pp.69, 1994.
[21] A. Nishiyama, O. Arisumi, and M. Yoshimi, “Suppression of the floating-body effect in partially-depleted SOI MOSFET’s with SiGe source structure and its mechanism,” IEEE Trans. Electron Devices, vol. 44, pp. 2187, 1997.
[22] M. C. Öztürk, J. Liu, H. Mo, and N. Pesovic, “Advanced Si1-xGex Source/Drain and Contact Technologies for sub-70 nm CMOS,” IEDM, pp. 375, 2002.
[23] P. Ranade, H. Takeuchi, V. Subramanian, and T. J. King, “A Novel Elevated Source/Drain PMOSFET Formed by Ge-B/Si Intermixing,” IEEE Electron Device Lett., vol. 23, pp. 218, 2002.
[24] H. Takeuchi, W. C. Lee, P. Ranade, and T. J. King, “Improved PMOSFET Short-Channel Performance Using Ultra-Shallow Si0.8Ge0.2 Source/Drain Extensions,” IEDM, pp. 501, 1999.
[25] T. Uchino et al., “A raised source/drain technology using in-situ P-doped SiGe and B-doped Si for 0.1-μm CMOS ULSIs,” IEDM Tech. Digest, pp.479, 1997.
[26] H. J. Huang, K. M. Chen, C. Y. Chang, L. P. Chen, G. W. Huang, and T. Y. Huang, “Reduction of source/Drain Series Resistance and Its Impact on Device Performance for PMOS Transistors with Raised Si1-xGex Source/Drain,” IEEE Electron Device Lett., vol. 21, pp. 448, 2000.
[27] A. Nishiyama, K. Matsuzawa, and S. I. Takagi, “SiGe Source/Drain Structure for the Suppression of the Short-Channel Effect of Sub-0.1-mm p-Channel MOSFETs,” IEEE Trans. Electron Device, vol. 48, pp. 1114, 2001.
[28] 廖偉明,“高效能矽鍺互補型金氧半電晶體之研製”,碩士論文,國立中央大學,民國91年。
[29] D. –X. Xu, “n-Si/p-Si1-xGex/n-Si double-heterojunction bipolar transistor,” Appl. Phys. Lett., vol. 52, pp. 2239, 1988.
[30] J. W. Coburn, and E. Kay, “Some Chemical Aspects of Fluorocarbon Plasma Etching of Silicon and Its Compounds,” Solid State Technol., pp. 117, 1979.
[31] J. W. Coburn, “Surface-science Aspects of Plasma-assisted Etching,” Appl. Phys. A, vol. A59, pp. 451, 1994.
[32] M. M. Millard, and E. Kay, “Difluocarbene Emission Spectra from Fluorocarbon Plasmas and Its Relationship to Fluorocarbon Polymer Formation,” J. Electrochem. Soc., pp. 160, 1982.
[33] 佳霖科技於本校STS ICP ETCHER與smart-EPDTM教育訓練課程中提供的資料。
[34] http://smithsonianchips.si.edu/ice/cd/MEM96/SEC13.pdf
[35] T. –J. King, and K. C. Saraswat, “Deposition and Properties of Low-Pressure Chemical-Vapor Deposited Polycrystalline Silicon-Germanium Films,” J. Electrochem. Soc., vol.141, pp. 2235, 1994.
指導教授 李佩雯(Pei-Wen Li) 審核日期 2004-7-16
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