博碩士論文 91521042 詳細資訊




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姓名 曾祈賓(Chi-Ping Tseng)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 矽鍺/矽異質接面動態啓始電壓金氧半電晶體之研製
(Fabrication of SiGe/Si Hetrojunction Dynamic Threshold Voltage MOSFETs)
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摘要(中) 摘 要
在本論文中,我們利用矽鍺/矽異質結構,實際製作出有Si1-xGex(x = 0、0.3)通道層的動態啓始電壓金氧半電晶體(Dynamic Threshold Voltage MOSFET,DTMOS)及一般金氧半電晶體(standard MOS)。並且分別在溫度為77K、150K、300K、320K、350K時,量測其直流特性表現,然後去比較溫度對DTMOS及standard MOS的影響。
在我們實際量測結果中,可看出SiGe DTMOS擁有比Si standard MOS高的驅動電流、大的轉導值、低的靜態漏電流及理想的次臨限斜率。而在溫度效應方面,SiGe DTMOS的啓始電壓及次臨限斜率對溫度的變化比standard MOS來得小,在高溫時,元件特性劣化的程度也比standard MOS來得小,所以SiGe DTMOS對溫度的穏定性比較好。
從以上SiGe DTMOS所擁有的優點來看,SiGe DTMOS的確是具有在低電壓、低功率及高速應用方面的潛力。
摘要(英) Abstract
In this thesis, we have demonstrated a high performance Si1-xGex(x = 0、0.3)DTMOS for low voltage、low power and high speed device applications. Measured the DC performance and compared the temperature effect between DTMOS and standard MOS at 77K、150K、300K、320K and 350K, respectively。
In our measurement, we had found that the SiGe DTMOS has higher drive current、greater transconductance、lower leakage current and ideal subthreshold slope than standard MOS. Beside, the threshold voltage and subthreshold slope of SiGe DTMOS have less sensitive for temperature than that of standard MOS. At high temperature, the degradation of SiGe DTMOS performance had lower than Si standard MOS. Therefore, SiGe DTMOS had better stability for temperature.
According to the above advantage, SiGe DTMOS have the potential in low voltage、low power dissipation and high speed application.
關鍵字(中) ★ 矽鍺異質接面動態啓始電壓金氧半電晶體
★ 矽鍺
★ 金氧半電晶體
關鍵字(英) ★ SiGe HDTMOS
★ SiGe
★ MOS
論文目次 目錄
摘要…………………………………………………………………Ⅰ
致謝…………………………………………………………………Ⅱ
圖目錄………………………………………………………………Ⅲ
表目錄………………………………………………………………Ⅷ
序章 論文結構介紹………………………………………………Ⅹ
第一章 介紹…………………………………………………………1
1-1 前言……………………………………………………………1
1-2 研究動機………………………………………………………2
1-3 研究目的與應用………………………………………………3
第二章 DTMOS原理介紹……………………………………………11
2-1 前言……………………………………………………………11
2-2 DTMOS結構與操作方式介紹……………………………………11
2-3 Body Effect Factor…………………………………………13
2-4 DTMOS在變溫下之特性原理……………………………………14
2-4-1 溫度與啓始電壓之關係……………………………………16
2-4-2 溫度與次臨限斜率之關係…………………………………17
2-5 結論………………………………………………………………18
第三章 元件製程之最佳化…………………………………………22
3-1 前言………………………………………………………………22
3-2 閘極線寬的縮小…………………………………………………23
3-3 金屬製程最佳化…………………………………………………24
3-3-1 真空蒸鍍與濺鍍之比較……………………………………25
3-3-2 運用鋁矽銅合金改善尖峰效應……………………………30
3-5 結論………………………………………………………………32
第四章 DTMOS之電性量測與分析……………………………………44
4-1 前言………………………………………………………………44
4-2 DTMOS與Standard MOS之特性比較………………………………45
4-3 通道長度對DTMOS特性的影響……………………………………50
4-4 DTMOS在變溫下之特性表現………………………………………52
4-5 結論………………………………………………………………55
第五章 結論與未來展望………………………………………………71
參考文獻資料…………………………………………………………72
參考文獻 參考文獻資料
[1] Fariborz Assaderaghi, Member, IEEE, Dennis Sinitsky, Stephen A. Parke, Jeffrey Bokor, Ping K. Ko, Fellow, IEEE, and Chenming Hu, Fellow, IEEE, “Dynamic Threshold-Voltage MOSFET(DTMOS)for Ultra Low Voltage VLSI,” IEEE Trans. Electron Device, vol. 44, no. 3, pp.414-422, 1997.
[2] Fariborz Assaderaghi, Stephen Parke, Member, IEEE, Dennis Sinitsky, Jeffrey Bokor, Member, IEEE, Ping K. Ko, Senior Member, IEEE, and Chenming Hu, Fellow, IEEE, “A Dynamic Threshold Voltage MOSFET(DTMOS)for Very Low Voltage Operation,” IEEE Electron Device Lett., vol. 15, no. 12, pp.510-512, 1994.
[3] Fariborz Assaderaghi, “DTMOS:Its Derivatives and Variations, and Their Potential Applications,” The 12th International Conference on Microelectronics, pp. 9-10, 2000.
[4] Fariborz Assaderaghi, Dennis Sinitsky, Stephen Parke, Jeffrey Bokor, Ping K. Ko, and Chenming Hu, “A Dynamic Threshold Voltage MOSFET(DTMOS)for Ultra Low Voltage Operation,” IEDM Tech. Dig., pp.809-812, 1994.
[5] T. Takagi, A. Inoue, Y. Hara, Y. Kanzawa, and M. Kubo, “A Novel High Performance SiGe Channel Heterostructure Dynamic pMOSFET(HDTMOS),” IEEE Electron Device Lett., vol. 22, no. 5, pp.206-208, 2001.
[6] Takahiro Kawashima, Yoshihiro Kanzawa, Haruyuki Sorada, Akira Asai, and Takeshi Takagi, “A Novel Low Voltage N-Channel Heterostructure Dynamic Threshold Voltage MOSFET(N-HDTMOS)With p-Type Doped SiGe Body,” IEEE Electron Device Lett., vol. 25, no. 1, pp.28-30, 2004.
[7] Jae-Ki Lee, Nag-Jong Choi, Chong-Gun Yu, Jean-pierre Colinge, Jong-Tae Park, “Temperature dependence of DTMOS transistor characteristics,” Solid-State Electronics, vol. 48, pp.183-187, 2004.
[8] Makoto Takamiya, Member IEEE, and Toshiro Hiramoto, Member IEEE, “High Drive-Current Electrically Induced Body Dynamic Threshold SOI MOSFET(EIB-DTMOS)With Large Body Effect and Low Threshold Voltage,” IEEE Trans. Electron Device, vol. 48, no. 8, pp.1633-1640, 2001.
[9] H. Kotaki, S. Kakimoto, M. Nakano, T. Matsuoka, K. Sugimoto, T. Fukushima and Y. Sato, “Novel Bulk Dynamic Threshold Voltage MOSFET(B-DTMOS) with Advanced Isolation(SITOS)and Gate to Shallow-Well Contact(SSS-C)Processes for Ultra Low Power Dual Gate CMOS,” in IEDM 1996, pp.459-462.
[10] Christopher R. Landry, “Double-Gate MOSFET:Operation and Threshold Voltage Control” ECE 612 Final Report, pp.1-9, 2003.
[11] Neamen, “Semiconductor Physics & Devices,” p.149
[12] Guido Groeseneken, Member, IEEE, Jean-Pierre Colinge, Senior Member, IEEE, Herman E. Maes, Senior Member, IEEE, J. C. Alderman, and S. Holt,“Temperature Dependence of Threshold Voltage in Thin-Film SOI MOSFET’s,” IEEE Electron Device Lett., vol. 11, no. 8, pp.329-331, 1990.
[13] Peter Van Zant 著, 姜庭隆譯, “半導體製程,” pp.418-433
[14] 莊逹人編著, “VLSI製造技術,” pp.146-178
[15] 廖偉明, “高效能矽鍺互補型金氧半電晶體之研製,” 碩士論文, 國立中央大學, 民國91年.
[16] Jae-Ki Lee, Nag-Jong Choi, Chong-Gun Yu, Member, IEEE, Jean-Pierre Colinge, Fellow, IEEE, and Jong-Tae Park, Member, IEEE,“Temperature Dependence of Hot-Carrier Degradation in Silicon-on-Insulator Dynamic Threshold Voltage MOS Transistors,” IEEE Electron Device Lett., vol. 23, no. 11, pp.673-675, 2002.
[17] Makoto Takamiya and Toshiro Hiramoto, “High performance Electrically Induced Body Dynamic Threshold SOI MOSFET(EIB-DTMOS)with Large Body Effect and Low Threshold Voltage,” in IEDM 1998, pp.423-426.
指導教授 李佩雯(Pei-Wen Li) 審核日期 2004-7-16
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