In the verification process, debugging is also a hard and time-consuming process and is often done by designers themselves. Because most design errors occur in the early design stages, there are also some approaches proposed for debugging HDL designs. The authors in  proposed a method to give a rank to each error candidate such that the efforts of debugging can be reduced because designers only have to trace several items in the front of list. However, due to lack of internal information of the circuit, the estimation of error possibility may still not very accurate. In this paper, we propose a method to use the extra observability provided by assertions to make a better estimation of error possibility. Using our approach, the error ranking can be more accurate than that in previous approach such that the debugging efforts can be further reduced. The effectiveness of our improvements can be shown in the experiments.
 M. S. Abadir, Y. M. Wang, and T. E. Kirkland, “Logic design verification via test generation”, in IEEE transactions on CAD, 7(1): 138-148, January 1988.
 D. Brand, “Incremental synthesis”, in Proceeding of Intl. Conference on Computer Aided Design, 1992, pp. 126-129.
 M. Tomita, T. Yamamoto, F. Sumikawa and K. Hirano, “Rectification of multiple logic design errors”, in Proceeding of ACM/IEEE DAC, 1994, pp. 212-217.
 D.W. Hoffmann and T. Kropf, “Efficient Design error correction of digital circuits “, in Proceeding of Intl. Conference on Computer Design, 2000, pp. 465-472.
 V. Boppana, I. Ghosh, R. Mukherjee, J. Jain and M. Fujita, “Hierarchical error diagnosis targeting RTL circuit”, in Proceeding of Intl. Conference on VLSI Design, 2000, pp. 436-441.
 Maisaa Khalil, Yves Le Traon, and Chantal Robach, “Towards an Automatic Diagnosis for High-level Validation”, in Proceeding of Intl. Test Conference, 1998, pp. 1010-1018.
 Tai-Ying Jiang; Chien-Nan Jimmy Liu; and Jing-Yang Jou, “Effective Error Diagnosis for RTL Design in HDLs”, in Proceeding of Asian Test Symposium (ATS ’02), Nov. 2002, pp: 362-367.
 Harry Foster, Adam Krolnik, David Lacey, “Assertion-Based Design”, Kluwer Academic Publishers, June, 2003.
 Ben Cohen, “Using PSL/Sugar with Verilog and VHDL, Guide to Property Specification Language for Assertion-Based Verification”, VhdlCohen Publishing, Los Angeles, California