應用於三元內容定址記憶體之低功率設計與測試技術

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姓名

林周坤(Chou-Kun Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於三元內容定址記憶體之低功率設計與測試技術
(Low-Power Design and Test Techniques for Ternary Content Addressable Memories)

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摘要(中)

功率消耗和電路面積是三元內容定址記憶的兩個主要設計要點。本論文提供一個10顆電晶體靜態元件和一個三元內容定址記憶體低功率設計方法。我們所提出的10顆電晶體的靜態元件可以以很低的面積費用去實作三元內容定址記憶體。與一個傳統9顆電晶體的靜態二元內容定址記憶體元件比較，我們只需要一個附加電晶體便可實現一個三元內容定址記憶體元件。由實驗結果得知一個10顆電晶體的靜態元件僅僅需要13.83um2面積。同時我們提出一個低功率設計技術，透過把一個字大小的命中線分成若干個疊接小命中線去減少搜尋功率消耗。模擬結果顯示針對一個32 x 64三元內容定址記憶體，當我們分割為８段時，且空白分段比例達到37.5%以上，我們將得到10%~70%功率減少量。
另一方面，由於三元內容定址記憶體的特殊架構使得測試方法更為複雜。所以在本論文中我們發展以實體缺陷為基礎的功能錯誤模型，例如短路缺陷，開路缺陷，電晶體恆開缺陷和電晶體恆關缺陷。我們也提出以功能錯誤模型為基礎的March-like測試演算法。我們的演算法僅僅使用基本的三元內容定址記憶體功能─讀，寫和搜查並且從單一的HIT輸出點去觀察測試結果。我們的演算法針對位元的三元內容定址記憶體僅僅需要4N+2W搜尋操作，4N寫入操作和4N的抹除操作便可偵測100%比較錯誤偵測能力。

摘要(英)

Power dissipation and area cost are two major design concerns of the ternary content addressable memory (TCAM). This thesis presents a 10T static cell and a low-power design methodology for TCAMs. The proposed 10T cell makes a static TCAM be able to be implemented with very low area cost. Compared with a typical 9T static binary cell, only one additional transistor is needed to realize a static ternary cell. Experimental results show that the proposed 10T cell only need about 13.83um2. A low-power design technique is also proposed to reduce the Search power by dividing the match line of a word into multiple cascaded small match lines. Simulation results show that for a 32 x 64 TCAM, about 10%~70% Search power reduction can be achieved if the ratio of empty segments is higher than 37.5% and the segment width is 8.
On the other hand, testing TCAMs is very complicated due to their special structure. In this thesis we develop functional fault models based on physical defects, such as short defects, open defects, transistor stuck-on defects, and transistor stuck-off defects. We also propose a March-like test algorithm for TCAMs based on the proposed functional faults. The test algorithm only requires basic TCAM operations, Write, Search, and Erase, and the test response can be observed entirely from the single-bit Hit output. The test algorithm requires 4N+2W Search operations, 4N Write operations, and 4N Erase operations to cover 100% target comparison faults for an N x W-bit TCAM.

關鍵字(中)

★ 記憶體
★ 低功率
★ 測試
★ 低面積

關鍵字(英)

★ memory
★ testing
★ low power
★ CAM
★ low area
★ TCAM

論文目次

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Previous Work 2
1.3 Thesis Organization 4
Chapter 2 Overview of Content Addressable Memories 5
2.1 Typical CAM Architecture 5
2.2 CAM Types 7
Chapter 3 Low-Power and Low-Area Design Techniques for TCAMs 13
3.1 Low-Power Design Methodology 13
3.2 The Proposed 10T TCAM Cell 17
3.3 Experimental Results 23
Chapter 4 TCAM Testing 36
4.1 Functional Fault Models 36
4.2 Functional Test Algorithms 53
4.3 Analysis and Comparison 57
Chapter 5 Conclusions 61
Appendix 62
Reference 71

參考文獻

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指導教授

李進福(Jin-Fu Li)

審核日期

2004-7-15

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