博碩士論文 91623017 詳細資訊




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姓名 吳俊毅(Jiun-Yi Wu)  查詢紙本館藏   畢業系所 太空科學研究所
論文名稱 微波輻射計數位相關器之設計與實現
(Desgin and Implement the Digital Correlator of Digital Total Power Microwave Radiometer)
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摘要(中) 本篇論文主要在於探討36.5GHz微波輻射計之數位相關器的設計與實現,參考1999年Fischman文章中,由理論結果提出的類比數位轉換器解析度只需要2-3位元,即足以接近理想類比式微波輻射計的輸出特性。依據36.5GHz數位式微波輻射計設計規格中,於中頻中心頻率為500MHz,頻寬為20MHz,使用次諧波取樣(subharmonic sampling)技術,以六位元類比數位轉換器取樣頻率為40MHz,積分時間為0.5秒,進行數位相關器之設計與實現。
數位相關器主要架構由六位元平方器、三十二位元累加器、RS-232串列傳輸控制器與控制單元所組成,平方器使用改良式布斯乘法器、累加器使用十二位元前瞻進位加法器與二十位元計數器串接而成,主要目的在於提升運算速度,RS-232串列傳輸控制器與控制單元皆使用有限狀態機的設計結構。設計方式以Verilog硬體描述語言設計,使用FPGA(FLEX 10K100ARC240-1)實驗板實現,在接收程式設計以Borland C++ Builder設計,傳輸速率使用57600bps,可即時接收與控制數位相關器資料。
從以上數位相關器與接收程式的實現與量測,完成了數位相關器實現也具備與電腦介面的整合功能,未來目標朝著全系統量測以完成微波輻射計的原型機實現。
摘要(英) In this thesis, the digital correlator of a digital total power microwave radiometer at 36.5 GHz is designed and implemented. Fischman (1999) theoretically showed that just 2 or 3 bits for the A/D converter resolution are needed to maintain the performance of an ideal analog radiometer. According to the specification of the radiometer, the MF center frequency is 500MHz and its signal bandwidth is 20MHz. To design and implement the digital correlator, a subharmonic sampling technique is used to determine the sample frequency of the 6 bits A/D converter (40 MHz) and the integration time (0.5 s).
The architecture of the digital correlator includes a 6-bit squarer, a 32-bit accumulator, a RS-232 UART and a control unit. The 6-bit squarer is designed by a modified Booth multiplier, and the 32-bit accumulator is designed by 12-bit Carry look-ahead adder and 20-bit counter. The purpose of the squarer and the accumulator is to improve the calculation speed. The RS-232 UART and the control unit are based on the finite state machine architecture. All of these components are designed using the Verilog hardware description language and implemented by a FPGA experimental board (Flex 10K100ARC240-1). The receiver program, implemented using the Borland C++ builder, can set the maximum transfer rate at 57600bps and can control and receive data from the correlator in real time.
Finally the digital correlator and the receiver program are implemented. The digital correlator is successful to communicate with computer. Future work will involve the full system measurement to complete the prototype of the digital total power microwave radiometer at 36.5 GHz.
關鍵字(中) ★ 數位相關器
★ 微波輻射計
★ FPGA
★ Verilog
★ 硬體描述語言
★ IC設計
關鍵字(英) ★ Digital Correlator
★ Microwave radiometer
★ FPGA
★ Verilog
★ Hardware description language
★ IC design
論文目次 1-1 研究目的 1
1-2 文獻回顧 2
1-2-1 輻射計簡介 2
1-2-2 輻射計原理 3
1-2-3 全功率數位輻射計 7
1-2-4 輻射計的數位分析 11
1-3 論文介紹 30
1-3-1 數位相關器設計原理 30
1-3-2 論文綱要 31
第二章 平方累加器的實現 33
2-1 平方器設計原理 33
2-1-1 改良式布斯演算法 33
2-1-2 演算法的實現 39
2-2 平方器模擬與實測結果 43
2-3 累加器設計原理 48
2-4 累加器模擬與實測結果 53
2-5 平方累加器整合測試 56
第三章 控制單元與串列傳輸控制器的實現 61
3-1 控制單元設計原理 61
3-2 串列傳輸控制器設計原理 65
3-3 控制單元與串列傳輸控制器模擬結果 71
第四章 數位相關器與介面接收程式的實現 76
4-1 數位相關器的自我測試結果 76
4-2 介面接收程式架構 85
4-3 數位相關器與介面接收程式整合測試 89
第五章 結論 96
參考文獻 98
附錄一 數位相關器邏輯線路圖 100
參考文獻 [1] F. T. Ulaby, R. K. Moore, and A. K. Fung, Microwave Remote Sensing: Active and Passive, Volume , Microwave Remote Sensing,Fundamentals and Radiometry, Addison- Wesley, 1981.
[2] J.-P. Wigneron, J.-C. Calvet, D. Guyon, G. Courrier, and O. Grojean, "Estimation of coniferous forest characteristics from passive microwave measurements." Proc.of IGARSS'95 Geoscience and Remote Sensing Symposium 'Quantitative Remote Sensing for Science and Applications', Firenze, 1995.
[3] N. Skou, Microwave Radiometer Systems: Design and Analysis, Norwood, MA: Artech House, 1989.
[4] M. A. Fischman and A.W. England, "An L-band direct sampling digital radiometer for STAR technology sensors," In Proc.of Aerospace Conference, Big Sky, MT, 2000.
[5] A. Pärssinen, R. Magoon, S. I. Long, and V. Porra, "A 2-GHz Subharmonic Sampler for Signal Downcoversion," IEEE Transactions on Microwave Theory and Techniques, Vol. 45, No. 12, Dec. 1997.
[6] 王詩傑, "36.5 GHz 微波輻射器接收模組之研製,“ 國立中央大學電機工程所碩士論文, 2003.
[7] M. A. Fischman and A.W. England, "Sensitivity of a 1.4 GHz Direct-Sampling Digital Radiometer," IEEE Transactions on Geoscience and Remote Sensing, vol. 37, No. 5, Sep. 1999.
[8] B. Sklar, Digital Communication, Upper Saddle River, NJ:Prentice -Hall, 1988, ch.1, p.17.
[9] R. E. Ziemer and W. H. Tranter, Principles of Communications: Systems, Modulation, and Noise, John Wiley & Sons, 1995.
[10] A. R. Cooper, "Parallel Architecture Modified Booth Multiplier", IEE Proceedings, Vol. 135, Pt G, No.3, June 1988.
[11] W. Stallings, Computer Organization and Architecture: Designing for Performance, Upper Saddle River, NJ:Prentice-Hall, 2000, ch. 8, p. 291.
[12] A. Wu, C. K. Ng , and K. C. Tang, "Modified Booth Pipelined Multiplication," IEE Electronics Letters, Vol. 34, pp. 1179-1180, June 1998.
[13] M. M. Mano and C. R. Kime, Logic and Computer Design Fundamentals, NY: Prentice Hall, 1997.
[14] D. R. Smith and P. D. Franzon, Verilog Styles for Synthesis of Digital Systems, Upper Saddle River, NJ: Prentice Hall, 2000, ch. 3, p. 28-31.
[15] F. Elguibaly, "A Fast Parallel Multiplier-Accumulator Using the Modified Booth Algorithm," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 47, No.9, Sep. 2000, pp. 902-908.
[16] D. R. Smith and P. D. Franzon, Verilog Styles for Synthesis of Digital Systems, Upper Saddle River, NJ: Prentice Hall, 2000, ch. 8, p. 119-120.
[17] S. Palnitkar, 黃英叡, 黃稚存, 張銓淵, 江文啟編譯, Verilog 硬體描述語言, 全華科技圖書股份有限公司, 2003.
[18] 范逸之, 江文賢, 陳立元編著, C++ Builder 與 RS-232 串列通訊控制, 文魁資訊股份有限公司, 2003.
[19] D. R. Smith and P. D. Franzon, Verilog Styles for Synthesis of Digital Systems, Upper Saddle River, NJ: Prentice Hall, 2000, ch. 8, p. 121-124.
[20] M. M. Mano, Computer System Architecture, Englewood Cliffs, NJ:Prentice-Hall, 1993, ch. 11, p. 400-402.
指導教授 劉說安、丘增杰
(Yuei-An Liou、Tsen-Chieh Chiu)
審核日期 2005-10-12
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