博碩士論文 92323105 詳細資訊




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姓名 陳維章(Wei-Chang Chen)  查詢紙本館藏   畢業系所 機械工程學系
論文名稱 使用FPGA設計之模糊控制IC實現在剛性攻牙
(FPGA-based Fuzzy Control IC on Rigid tapping)
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摘要(中) 本論文提出一個整合FPGA為基礎之模糊控制器,應用於機械加工控制CNC工具機之剛性攻牙(Rigid tapping)。利用現場可程式邏輯閘陣列(FPGA)去完成CNC加工之電路。此顆模糊控制晶片運用現場可程式邏輯閘陣列的技術來製作,並以選擇SRAM為基礎之FPGA來完成。FPGA有下列優點:不必修改週邊之硬體電路即可進行電路修改和可增加額外之功能等。
本論文之模糊控制晶片包含模糊化電路、規則庫電路、推論工場電路及解模糊化電路等主要電路模組,結合馬達控制電路外,還整合了光編碼器電路、馬達驅動訊號電路,採高度模組化設計,利用全球通用且跨平台之VHDL硬體描述語言設計。藉用FPGA發展軟體模擬所設計之電路之功能性與可行性,再實際與工具機連結,以進行CNC剛性攻牙之實驗。
藉由FPGA可重覆燒錄的特性,使用Xilinx公司發展的軟體,可以很容易撰寫VHDL程式,並搭配Modelsim做時序圖的模擬,將程式燒錄到FPGA和硬體結合,可以很方便的做結果測試,然後對照實驗結果去做程式的修改,可以節省時間和大幅降低成本,這對研發的時間和成本是十分有利的。
摘要(英) This thesis will apply a fuzzy logic controller to develop a new circuit realization to perform manufacture for a CNC machine rigid tapping. A field programmable gate array (FPGA) will be used to develop for manufacture. It will be developed by using FPGA with SRAM for manufacture. Using FPGA has many advantages such as easy circuit modification and performance expansion. The fuzzy logic control system in this thesis consists of fuzzification circuit, rule-base circuit, inference circuit, defuzzification circuit. Combined with the photo encoder circuit, motor driver circuit, design with module. VHDL will be used to design. A FPGA developing software system will simulate the designed circuit to test the performance and feasibility. Finally a CNC machine tool used will perform CNC manufacture. It can cover and burn the characteristic recorded again with FPGA. Using the software of Xilinx Company’’s development can be very apt to write VHDL program and match the simulation that Modelsim did the chronological chart. Burning the program and record to FPGA and hardware combining can be very convenient to do the result to test. Modifying experimental result and the program can save time and lower costs to achieve good performance.
關鍵字(中) ★ 剛性攻牙
★ 現場可程式邏輯閘陣列
★ 模糊控制
關鍵字(英) ★ fuzzy control
★ FPGA
★ rigid tapping
論文目次 摘 要 I
致 謝 II
目 錄 III
第一章 導 論 IV
第二章 控制器的設計 V
第三章 FPGA之簡介 VI
第四章 精密位置控制IC之實現 VII
第五章 實驗結果與討論 VIII
第六章 結 論 IX
附 錄 X
ABSTRACT XI
CONTENTS XII
LISTS OF FIGURES XIV
TABLE XVI
CHAPTER 1 INTRODUCTION 1
1.1 BACKGROUND AND MOTIVATION 1
1.2 LITERATURE SURVEY 1
1.3 AIM OF THE THESIS 3
CHAPTER 2 CONTROLLER DESIGN 5
2.1 FUZZY SETS AND FUZZY LOGIC 5
2.2 FUZZY REASONING 7
2.3 CONCEPT OF THE CONTROL SYSTEM 8
2.4 CONTROLLER DESIGN 10
2.4.1 General Control Scheme 12
2.4.2 Construction of The Rule Base 13
2.4.3 Fuzzy Inference Engine 14
CHAPTER 3 GENERAL DESCRIPTION OF FPGAS 15
3.1 OVERVIEW OF FPGAS 15
3.2 FPGA ARCHITECTURE 16
3.2.1 Configurable Logic Blocks 16
3.2.2 Input/Output Block 17
3.3 DESIGN PROCESS OF THE FPGA 18
CHAPTER 4 REALIZATION OF FUZZY LOGIC CONTROL IC 21
4.1 THE OVERVIEW OF FUZZY LOGIC CONTROL IC 21
4.2 QUADRATURE DECODERS AND UP/DOWN COUNTERS 21
4.3 POSITION COMMAND DECODERS 23
4.4 PARALLEL TO SERIAL CIRCUIT 23
4.5 CONTROL CIRCUIT 25
4.5.1 Fuzzification 26
4.5.2 Knowledge Base 28
4.5.3 Inference Engine 30
4.5.4 Defuzzification 32
CHAPTER 5 RESULTS OF SIMULATION AND EXPERIMENT 34
5.1 EXPERIMENT SYSTEM 34
5.2 EXPERIMENT RESULTS OF FUZZY CONTROL CIRCUIT 36
CHAPTER 6 CONCLUSIONS AND FUTURE WORK 40
6.1 CONCLUSIONS 40
6.2 FUTURE WORK 40
REFERENCE 42
Lists of Figures
Figure 2-1 Union 5
Figure 2-2 intersection 6
Figure 2-3 Complement 6
Figure 2-4 A frame of GMP. 7
Figure 2-5 The process of fuzzy reasoning. 8
Figure 2-6 Membership function for variable temperature 9
Figure 2-7 General block diagram of the controller. 11
Figure 2-8 A frame of output of fuzzy logic controller. 11
Figure 2-9 Block diagram of fuzzy logic controller 12
Figure 3-1 Architecture of CLB (adapted from Xilinx databook) 17
Figure 3-2 Input/Output Block (adapted from Xilinx databook) 18
Figure 3-3 Design flow chart of the FPGA. 19
Figure 4-1 The architecture fuzzy logic control IC. 21
Figure 4-2 Block diagram of quadrature decoder and up/down counter. 22
Figure 4-3 Block diagram of digital filter. 22
Figure 4-4 The simulation result of quadrature decoders and counters. 23
Figure 4-5 The waveform of pulse command. 23
Figure 4-6 AD1866 control signals. 24
Figure 4-7 Parallel to Serial D/A circuit. 24
Figure 4-8 The simulation result of parallel to serial D/A circuit. 25
Figure 4-9 Block diagram of fuzzy logic control circuit. 25
Figure 4-10 Membership function of error and rate of change of error. 26
Figure 4-11 One input touch off membership function with two value 27
Figure 4-12 A frame of fuzzification circuit. 27
Figure 4-13 Output membership functions of the fuzzy controller. 28
Figure 4-14 A frame of rule table circuit. 29
Figure 4-15 A frame of touch off membership function. 30
Figure 4-16 The definition of knowledge base. 30
Figure 4-17 Min-max inference. 31
Figure 4-18 A frame of inference engine circuit. 32
Figure 4-19 A frame of defuzzification circuit. 33
Figure 4-20 The module of fuzzy control. 33
Figure 5-1 The Pou Yuen machine tool. 34
Figure 5-2 FPGA emulation board. 35
Figure 5-3 Schematic of D/A converter. 36
Figure 5-4 A frame of compare circuit. 36
Figure 5-5 The simulation of compare circuit 36
Figure 5-6 The RTL view of compare circuit. 37
Figure 5-7 The simulation of rule base circuit. 37
Figure 5-8 The RTL view of rule base circuit. 37
Figure 5-9 The simulation of divider circuit. 38
Figure 5-10 The RTL view of divider circuit. 38
Figure 5-11 The simulation of fuzzy control circuit. 39
Figure 5-12 The RTL view of fuzzy control circuit. 39
Table
Table I A storing chart of membership function 27
Table II The membership function of consequent. 28
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指導教授 董必正(Pi-Cheng Tung) 審核日期 2005-9-27
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