參考文獻 |
[1] Y. Zorian, “Guest editor's introduction: what is infrastructure IP?”, IEEE Design & Test of Computers, vol. 19, May-June 2002, pp. 3 – 5.
[2] Y. Zorian, “Guest editor's introduction: Advances in infrastructure IP”, IEEE Design & Test of Computers, vol. 20, May-June 2003, pp. 49 – 49.
[3] Y. Zorian, “Infrastructure IP for SOC”, in Proc. IEEE VLSI Test Symposium, April 2004, pp. 0_23 - 0_23.
[4] P. Mazumder, and J. S. Yih, “A novel built-in self-repair approach to VLSI memory yield enhancement”, in Proc. International Test Conference, Sept. 1990, pp. 833 – 841.
[5] A. Tanabe, T. Takeshima, H. Koike, Y. Aimoto, M. Takada, T. Ishijima, N. Kasai, H. Hada, K. Shibahara, T. Kunio, T. Tanigawa, T. Saeki, M. Sakao, H. Miyamoto, H. Nozue, S. Ohya, T. Murotani, K. Koyama, and T. Okuda, ”A 30-ns 64-Mb DRAM with built-in self-test and self-repair function”, IEEE Journal of Solid-State Circuits, vol. 27, Nov. 1992, pp. 1525 – 1533.
[6] T. Chen, and G. Sunada, “Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, June 1993, pp. 88 – 97.
[7] P. Mazumder, and Y.-S. Jih, “A new built-in self-repair approach to VLSI
memory yield enhancement by using neural-type circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, Jan. 1993, pp. 124 – 136.
[8] Ilyoung Kim, Y. Zorian, G. Komoriya, H. Pham, F.P. Higgins, and J.L. Lewandowski, “Built in self repair for embedded high density SRAM”, in Proc. International Test Conference, Oct. 1998, pp. 1112 – 1119.
[9] D. K. Bhavsar, “An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264”, in Proc. International Test Conference, Sept. 1999, pp. 311 – 318.
[10] H.-C. Kim, D.-S. Yi, J.-Y. Park, and C.-H. Cho, “A BISR (built-in self-repair) circuit for embedded memory with multiple redundancies”, in Proc. International Conference onVLSI and CAD, Oct. 1999, pp. 602 – 605.
[11] N. Park, and E. Lombardi, “Repair of memory arrays by cutting”, in Proc. International Workshop on Memory Technology, Design and Testing, Aug. 1998, pp. 124 – 130.
[12] S.-K. Lu, and C.-H. Hsu, “Built-In self-repair for divided word line memory”, in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), vol. 4, May 2001, pp. 13 – 16.
[13] T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in self-repair analyzer (CRESTA) for embedded DRAMs”, in Proc. International Test Conference, Oct. 2000, pp. 567 – 574.
[14] J. Ohtani, T. Ooishi, T. Kawagoe, M. Niiro, M. Maruta, and H. Hidaka, “A shared built-in self-repair analysis for multiple embedded memories”, in Proc. IEEE Conference on Custom Integrated Circuits, May 2001, pp. 187 – 190.
[15] Y. Nagura, M. Mullins, A. Sauvageau, Y. Fujiwara, K. Furue, R. Ohmura, T. Komoike, T. Okitaka, T. Tanizaki, K. Dosaka, K. Arimito, Y. Koda, and T. Tada, “Test cost reduction by at-speed BISR for embedded DRAMs”, in Proc. International Test Conference, Oct. 2001, pp. 182 – 187.
[16] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Built-in redundancy analysis for memory yield improvement”, IEEE Transactions on Reliability, vol. 52, Dec. 2003, pp. 386 – 399.
[17] J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu, “A built-in self-repair scheme for semiconductor memories with 2-D Redundancy”, in Proc. International Test Conference, vol. 1, Sept. 2003, pp. 393 – 402.
[18] Xiaogang Du, S.M. Reddy, W.-T. Cheng, J. Rayhawk, and N. Mukherjee, “At-speed built-in self-repair analyzer for embedded word-oriented memories”, in Proc. International Conference on VLSI Design, 2004, pp. 895 – 900.
[19] R.-F. Huang, C.-L. Su, and Cheng-Wen Wu, “Fail pattern identification for memory built-in self-repair”, in Proc. Asian Test Symposium (ATS), Nov. 2004, pp. 366 – 371.
[20] C.-L. Su, R.-F. Huang, and C.-W. Wu, “A processor-based built-In self-repair design for embedded memories”, in Proc. Asian Test Symposium (ATS), Nov. 2003, pp. 366 – 371.
[21] M. L. Bushnell, and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI circuits, 2000, pp. 286-295.
[22] R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu, “A simulator for evaluating redundancy analysis algorithms of repairable embedded memories”, in Proc. IEEE International Workshop on Memory Technology, Design, and Testing, July 2002, pp. 68-73.
[23] J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu, “A built-in self-repair design for RAMs with 2-D redundancies”, IEEE Transactions on VLSI Systems, vol.13, no.6, pp. 742-745, June, 2005.
[24] R. Rajsuman, “Testing a system-on-a-chip with embedded microprocessor”, in Proc. Internal Test Conference, pp. 499-508, 1999.
[25] C.-H. Tasi, C.-W. Wu, “Processor-programmable memory BIST for bus-connected embedded memories”, in Proc. IEEE Asia South Pacific Design Automation Conference (ASP-DAC), pp. 325-330, Jan, 2001. |