博碩士論文 92521019 詳細資訊




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姓名 劉孟堯(Meng-Yao Liu)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 用於類比/混和訊號積體電路可靠度增強的加壓測試
(Extreme Voltage Stress Test of Analog/Mixed Signal ICs for Reliability Enhancement)
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摘要(中) 極電壓加壓測試系統架構已經發展出來,用於降低由閘極氧化層缺陷引起所失去的產能。但是,這個為了閘極氧化層發展出來的測試架構是以1 /E模型為基礎,這樣的缺陷模型適合氧化層厚度超過5nm的製程。在實際設計與製程上,.18?m或者以下製程,氧化層厚度會低於5nm,因此1/E缺陷模型可能是不適用的。在這項研究過程中,我們將考慮E缺陷模型。在此,氧化層厚度介於2.7nm到18.1nm之間範圍均適用。因此,本徵氧化層崩潰的壽命和故障率可以在某一壓力條件下被預測。本論文也說明產生加壓向量並且對電路上可加壓度低落的部分予以提升。ㄧ個使用另加的硬體的可加壓度提升策略也被提出。
為了去證明發展的極電壓測試技術,我們對於CMOS SRAM和PLL電路進行加壓測試的過程與應用。它顯示兩個電路可以在一些電晶體存在閘極氧化層缺陷的情況下透過傳統的Iddq測試,造成可靠度低落。因此,半導體製造商使用其它的加壓測試,在昂貴的熱燒過程中試驗,提升閘極氧化層的可靠度。然而,若使用此論文發展的壓力測試向量,兩個電路可被完全加壓。因此,能使電路全部閘極氧化層在極電壓壓力下測試下達到完全可靠度而不需使用昂貴的熱燒試驗。
摘要(英) The framework of extreme-voltage stress test system has been developed to reduce the lost yield caused by gate-oxide defects. However, the framework was developed for the gate-oxide defects that assume with 1/E model, where such a defect model is applicable for the oxide thickness above 5nm. For practical designs with the process of .18 um or below, the oxide thickness is less than 5nm, and thus the defect model with 1/E model may not be applicable accurately. In this study, the defect model with E model will be considered, where the oxide thickness is ranged between 2.7nm to 18.1nm. Therefore, the lifetime and failure rate of intrinsic oxide breakdown can be predicted for a given stress condition.
This thesis demonstrates the methodology that generates the stress vector and deals with stressability enhancement of portions of the circuit having poor stressability. A stressability enhancement strategy using additional hardware is also presented.
In order to demonstrate the developed stress test generation process, we demonstrates the applications of such process to both CMOS SRAM and PLL. It will show that both circuits may pass the conventional Iddq-tests in the presence of gate-oxide defects that occur at some transistors, causing a low reliability. Therefore, semiconductor manufacturers need to take alternative stress tests, expensive burn-in tests, to enhance gate-oxide reliability. However, with the developed stress test vectors, both circuits are fully stressed. As a result, the circuit can achieve a full gate-oxide reliability under the extreme-voltage stress tests without the need of the expensive burn-in tests.
關鍵字(中) ★ 可靠度
★ 類比
★ 測試
★ 加壓
關鍵字(英) ★ stress
★ reliability
★ analog
★ test
論文目次 Chapter1 INTRODUCTION.................................................1
1.1 Motivation..............................................3
1.2 Organization............................................4
Chapter2 BRACKGROUND..................................................6
2.1 Physical Failure Mechanisms.............................6
2.1.1 Failure Mechanisms......................................6
2.1.2 CMOS Gate-Oxide Reliability.............................7
2.2 Defect Models...........................................10
2.2.1 Hole-Induced (1/E) Breakdown Model......................10
2.2.2 Thermochemical (E) Breakdown Model......................11
2.3 Extreme-Voltage Stress Tests............................12
2.4 Burn-in Tests...........................................16
2.5 Extreme-Voltage Stress Tests with 1/E model.............17
2.5.1 Stress Time and Stress Voltage..........................17
2.5.2 Stress Test Vector Generation...........................19
Chapter3 Stress Test of Analog Circuits with E model..................22
3.1 Stress Vector Generation................................22
3.1.1 Stress Test Vector Generation...........................23
3.1.2 Stress Time Calculation.................................24
3.2 Stressability Design Methodology........................26
3.2.1 Stressability Enhancement...............................26
3.2.2 Stress Time Reduction...................................28
3.2.3 Pin Overhead Reduction..................................34
Chapter4 Stress Test of CMOS Circuits for Reliability Enhancement.....39
4.1 Stress test for CMOS SRAM...............................39
4.1.1 SRAM Architecture and Its Component.....................39
4.1.2 Conventional Extreme-Voltage Stress Tests...............40
4.1.3 Developed Extreme-Voltage Stress Tests..................45
4.2 Stress Test for CMOS PLL................................53
4.2.1 PLL Architecture and Its Components.....................54
4.2.2 Conventional Extreme-Voltage Stress Tests...............59
4.2.3 Developed Extreme-Voltage Stress Tests..................62
4.3 Conclusion..............................................63
Chapter5 Conclusions and Future Work..................................67
5.1 Major Contributions.....................................67
5.2 Future Research Work....................................68
參考文獻...............................................................70
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指導教授 魏慶隆(Chin-Long Wey) 審核日期 2005-7-15
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