博碩士論文 92521020 詳細資訊




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姓名 黃俊豪(Jyun-Huo Haung)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 基於鎖相迴路之多重相位脈波產生器
(PLL Based Multi-Phases Clock Generator)
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摘要(中) 晶片操作頻率及傳輸頻寬的增加引起了數兆赫時脈的龐大需求。然而單一時脈的頻率卻受限於信號反射、耦合以及供應電源的彈跳。因此多相位時脈技術被發展用來增進訊號的完整性及可靠度。它使用N個相位時脈取代單一的高頻時脈,而且能使頻率減少至單一時脈頻率的1/N。然而,多相位時脈的分佈卻是一個挑戰。時脈的繞線增加額外的面積和時序的不確定性。
因此,我們提出一個創新的架構增進時序的效能以及減少繞線的面積。這個架構包含一個環形震盪器形式的鎖相迴路、相位打散器以及可調適四相位時脈信號產生器。雖然鎖相迴路的理論已經被深入發展,我們仍推導出實用的公式可以推算系統參數。多相位時脈由鎖相迴路產生而且靠著相位打散器傳遞,相位打散器被提出用來平均相位誤差。因為這個架構僅傳遞1/4數量的相位在時脈分佈上,繞線跟時脈信號緩衝器的功率消耗減少。
最後,可調適四相位時脈信號產生器被用在廣域的次模組電路。這個電路由單一時脈再生四相位時脈,而且由於我們加入回授設計使這個電路增進了更廣的操作頻率範圍。兩個鎖相迴路已經以台積電0.18微米1P4M CMOS製程與聯電0.13微米1P8M CMOS製程實作,而在此發表的多相位分佈架構將以聯電0.13微米1P8M CMOS製程設計。
摘要(英) Increases of chip operation frequency and transmission bandwidth result in a great demands for multi-GHz clocking. However the frequency of a single clocking is limited due to signal reflection, coupling, and supply bounce. Therefore, multi-phases clocking technique is developed to improve signal integrity and reliability. It uses N-phases clocking to replace single high frequency clocking, and can reduce frequency to 1/N of single clocking frequency. However, there is a challenge to the distribution of multi-phases clocking. The clocking routing increases the area overhead and timing uncertainty.
Therefore, we propose a novel architecture to improve timing performance and reduce routing area. This architecture includes a ring-oscillator-based PLL, phase blenders, and adaptive quadrature clock generator. Although the PLL theory has been well developed, we derive practical and useful equations to estimate system parameters. The multi-phases clocking is generated by PLL and delivered by phase blenders, which has been proposed to average phase error. Because this architecture only delivers 1/4 numbers of phases on clock distribution, routing area and power consumption of clock buffers is decreased.
Finally, the adaptive quadrature clock generators are employed in the global sub-module circuits. This circuit regenerates quadrature phases clocking from a single clocking and it has been improved to wider operation frequency range due to our feedback design. Two PLLs are implemented in tsmc 0.18μm 1P4M CMOS process and UMC 0.13μm 1P8M CMOS process, and the proposed multi-phases distribution architecture is designed in UMC 0.13μm 1P8M CMOS process.
關鍵字(中) ★ 鎖相迴路
★ 多重相位
關鍵字(英) ★ Phase-locked loop
★ multi-phases
論文目次 Chapter 1 Introduction 1
1.1 Thesis Motivation to Multi-phases Clocking Generator 1
1.2 Goal of This Thesis 2
1.3 Organization of This Thesis 4
Chapter 2 Priciples of Phase-Locked Loop 6
2.1 Introduction to PLL 6
2.1.1 Basic Operations in PLL 8
2.2 Brief History 9
2.3 PLL Architecture for Multi-phases Clocking 9
2.3.1 Phase / Frequency Detector and Charge Pump 11
2.3.2 Loop Filter 15
2.3.3 Voltage Controlled Oscillator and Interpolator 19
2.3.4 Divider 20
2.4 Analysis of PLL Linear Model 20
2.4.1 Performance in locked state 27
2.4.2 Acquisition 29
2.5 Performance Criteria and System Parameters 32
2.5.1 Loop bandwidth 33
2.5.2 Gain margin and phase margin 34
2.6 Summary 35
Chapter 3 Desing and Simulations of PLL 36
3.1 Behavioral Model Simulation 36
3.2 Circuit Implementation 45
3.2.1 Phase / Frequency Detector 46
3.2.2 Charge Pump 48
3.2.3 Loop Filter 50
3.2.4 Voltage Controlled Oscillator 50
3.2.5 Divider 57
3.3 Measurement Consideration 58
3.4 Simulations and Measurement Results 59
3.5 Noise and Jitter analysis 68
3.6 Summary 70
Chapter 4 Multi-phases Clock Generator Techique 71
4.1 Architecture of Multi-phases Clock Distribution 71
4.2 Quadrature Clock Generator 74
4.2.1 Interpolator 74
4.2.2 Duty Cycle Corrector 76
4.2.3 Adaptive Quadrature Clock Generator 78
4.3 Loop Analysis of Adaptive QCG 83
4.4 Summary 85
Chapter 5 Conclusions and Future Work 86
Bibliography 88
Appendix A. Formula Derivation 92
Appendix B. Architecture and Circuits of PLL-tsmc 93
Appendix C. Circuit Sizing of PLL 95
Appendix D. Simulation Results of QCG 98
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指導教授 鄭國興、周世傑
(Kuo-Hsing Cheng、Shyh-Jye Jou)
審核日期 2005-7-21
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