博碩士論文 92521025 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:23 、訪客IP:13.58.216.18
姓名 翁祥峰(Xiang-Feng Weng)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 高速無進位除法器設計
(On the Design of High Speed Carry-Free Dividers)
相關論文
★ 用於類比/混和訊號積體電路可靠度增強的加壓測試★ 應用於電容陣列區塊之維持比值良率的通道繞線法
★ 以正交分頻多工系統之同步的高效能內插法技術★ 增強CMOS鎖相迴路可靠度
★ 適用於地面式數位電視廣播系統之平行架 構記憶體式快速傅立葉轉換處理器設計★ 對於長解碼長度可降低其記憶體使用的低密度同位檢查碼解碼器設計
★ 單級降壓式功因修正轉換器之探索★ 設計具誤差消除機制之串疊式三角積分調變器
★ 交換電容式類比電路良率提升之設計方法★ 使用分級時序記憶實作視角無關手勢辨識問題
★ 部分平行低密度同為元檢查碼解碼器設計★ 應用於無線通訊系統之同質性可組態記憶體式快速傅立葉處理器
★ 低記憶體需求及效能改善的低密度同位元檢查碼解碼器架構★ 混合式加法器設計
★ 非線性鋰電池之充放電模型★ 降壓型轉換器之控制在市電併聯型光伏系統
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 在本篇論文中,將介紹除法器完整的設計和實現。主要是為了設計出一個高速基底4的除法器,利用數值重複循環的方式。一般傳統SRT除法器的商值是用PLA or ROM 實現,不僅花費時間長且面積龐大。本論文的演算法是利用拉大商值來擴大可選取的區域,來簡化選擇商值的電路設計。將商值分成二個部份去做運算,同時做二個不同商值的運算得到二個不同的餘數,再依據餘數做一次商值的選擇,得到正確的商數跟餘數。用此方法在商值的電路設計上會簡化許多而且會加快整體速度。此外 ,使用簡單的邏輯電路來實現商值電路且改善它的整體速度。最後,我們使用 0.18μm CMOS 製程來實現雙精準度除法,它整體運算時間為50.8ns。
摘要(英) The design of a fast divider is an important issue in high-speed computing. This study presents fast radix-4 SRT division architecture with the digit-recurrent approach. Digit-recurrent division is an algorithm in which the quotient is obtained one digit per iteration. In this study, instead of finding the correct quotient digit, an estimated quotient digit is first speculated. The speculated quotient digit is used to simultaneously compute the two possible partial remainders for the next step while the quotient digit is being corrected. Thus, this two-step process does not influence the overall speed. Since the decision making circuits can be implemented with simple gate structures, the proposed divider offers fast speed operation. Based on the physical layout, the circuit achieves 50.8ns for a double precision division (56 bits for fraction part), where the TSMC 0.18μm CMOS technology is employed and simulated.
關鍵字(中) ★ 除法器 關鍵字(英) ★ carry-free
★ divider
論文目次 Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Objectives 1
1.3 Organization 2
Chapter 2 Background 3
2.1 Iterative Division Methods 3
2.1.1 The Restoring Division 3
2.1.2 The Nonrestoring Division 4
2.1.3 The SRT Division 6
2.2 A Carry Free Divider 8
2.3 High-Radix SRT Division 10
2.4 A Radix-4 Carry-free Divider Design 16
2.5 Time-Delay and Power Dissipation 19
Chapter 3 Implementation 24
3.1 Radix-4 Carry-Free Divider Design 24
3.2 Developed Components 26
3.2.1 MCA2 Cell Implementation 28
3.2.2 MCA4 Cell Implementation 35
3.3 Experimental Results 37
Chapter 4 Conclusions and Future Work 40
References 42
參考文獻 [1] B. Parhami, Computer Arithmetic: Architecture and Hardware Design. New York, Oxford, 2000.
[2] C.L. Wey and C.P. Wang, “Design of a fast radix-4 SRT divider and its VLSI implementation.” IEE Proceedings, Computers and Digital Techniques, vol. 146, Issue 4, pp. 205-210, July 1999.
[3] T.K. Fachhochschule, “Design of a configurable speed optimized Radix-4 Hardware Divider.” Master Thesis, Carinthia Tech Institute University, July 2002.
[4] C.L. Wey, “Design of fast high-radix SRT dividers and their VLSI impl- ementation.” IEE Proceedings, Computers and Digital Techniques, vol. 147, Issue 4, pp. 275-282, July 2000.
[5] A.H. David, H.G. Jackson, R.A. Saleh, Analysis and Design of Digital Integ- rated Circuits, McGraw-Hill, USA, 2004.
[6] J.H. Won, and K. Choi, “Low power self timed radix-2 Division,” IEEE Proceedings Trans. on Computer Arithmetic, vol. 46, no. 1, Jan. 1997.
[7] Y. Jiang, A. Sheraidah, Y. Wang, E. Sha, and J.G. Chung, “A Novel Multipl- exer-Based Low Power Full Adder,” IEEE Trans. on Circuits and Systems, vol. 51, no. 7, July 2004.
[8] H.T. Bui, Y. Wang, and Y. Jiang , “Design and Analysis of Low Power 10-Transistor Full Adders Using Novel Xor-Xnor Gates,” IEEE Transactions on Circuits and Systems, vol. 49, no. 1, July 2002.
[9] M. Ercegovac, and T. Lang, “On-the-fly conversion of redundant into conventional representations,” IEEE Trans. on Computers, vol. 36, pp. 895-897, July 1987.
[10] C. Rowen, M. Johnson, and P. Ries, “The MIPS R3010 floating point coprocessor,” IEEE Micro, pp. 53-62, Jun. 1988.
[11] A. Nannarelli, T. Lang, “Low-power radix-4 combined division and square root.” Computer Design International Conference, pp.236 – 242, Oct. 1999 .
[12] S. Inui, T. Uesugi, H. Saito, Y. Hagihara, A. Yoshikawa, M. Nishida, M. Yamashina, “A 250 MHz CMOS floating-point divider with operand pre-scaling, ” Digest of Technical Symposium on VLSI Circuits, pp.17-19 Jun. 1999.
[13] A. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, T. Kwan, “The design of an asynchronous microprocessor,” in Proceedings Decennial Caltech Conference on VLSI, pp. 351-373, Mar. 1989.
[14] A. Nannarelli and T. Lang, “Low-Power Radix-8 Divider,” Proceedings of International Conference on Computer Design (ICCD), pp. 420–426, Oct. 1998.
[15] A. Nannarelli and T. Lang, “Low-Power Divider,” IEEE Trans. on Computers, pp. 2–14, Jan. 1999.
[16] A. Prabhu, and G. Zyner, “167 MHz radix-8 divide and square root using overlapped radix-2 stages,” Proceedings of 12th Symposium on Computer Arithmetic, pp. 155–162, July 1995.
[17] G. Taylor, “Radix-16 SRT dividers with overlapped quotient selection stages,” Proceedings of 7th Symposium on Computer Arithmetic, pp. 64–71, 1985.
[18] K. Usami, and M. Horowitz, “Clustered voltage scaling technique for low-power design,” Proceedings of International Symposium on Low Power Design, pp 3–8, Apr. 1995.
[19] P. Montuschi, and Luigi Ciminiera, “Design of a radix 4 division unit with simple selection table,” IEEE Trans. on Computers, Vol. 41, No.12, pp.1606-1611,Dec. 1992.
[20] M.D. Ercegovac, and T. Lang, “A division algorithm with prediction of quotient digits,” IEEE Proceedings, Symposium on Computer Arithmetic, pp.64-71, Jun. 1985.
[21] P. M. Seidel, “High-speed redundant reciprocal approximation,” Integration, the VLSI Journal, vol. 28, pp. 1–12, 1999.
[22] P. Montuschi, and T. Lang, “Boosting very-high radix division with prescaling and selection by rounding,” IEEE Trans. on Computers, vol. 50, pp. 13–27, Jan. 2001.
[23] M. D. Ercegovac and T. Lang, “A division algorithm with prediction of quotient digits,” IEEE Proceedings, Conference on Computer Design, pp. 51–56, Jan, 1985.
[24] T. E. Williams and M. A. Horowitz, “A zero-overhead self-timed 160-ns 54-b CMOS divider,” IEEE Journal of Solid-State Circuits, vol. 26, pp. 1651–1661, Nov.1991.
[25] R. Shalem, E. John, and L. K. John, “A novel low-power energy recovery full adder cell,” Proceedings Great Lakes Symposium on VLSI, pp.380–383, Feb. 1999.
[26] A. P. Chandrakasan, S. Sheng, and R. W. Broderson, “Low-power CMOS digital design,” IEEE Journal Solid-State Circuits, vol. 27, pp. 473–483, Apr. 1992.
[27] E. Antelo, T. Lang, P. Montuschi, T. Nannarelli, “A Digit-Recurrence Dividers with Reduced Logical Depth, ”Computers, IEEE Trans. vol 54, pp. 837 – 851, July 2005.
指導教授 魏慶隆(Chin-Long Wey) 審核日期 2005-7-19
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明